/external/llvm/test/CodeGen/Mips/llvm-ir/ |
D | ret.ll | 15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
D | ret.ll | 15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
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/external/v8/src/compiler/mips64/ |
D | instruction-scheduler-mips64.cc | 443 DMTC1 = 4, enumerator 749 return UldLatency() + Latency::DMTC1; in Uldc1Latency() 1024 Latency::DMFC1 + 1 + XorLatency() + Latency::DMTC1; in NegdLatency() 1122 3 * Latency::DMFC1 + OrLatency() + Latency::DMTC1 + Latency::MOV_D + in TruncUlDLatency() 1492 return 1 + Latency::DMTC1 + Latency::CVT_S_L; in GetInstructionLatency() 1494 return Latency::DMTC1 + Latency::CVT_S_L; in GetInstructionLatency() 1496 return Latency::DMTC1 + Latency::CVT_D_L; in GetInstructionLatency() 1498 return 1 + Latency::DMTC1 + Latency::CVT_D_L; in GetInstructionLatency() 1500 return 2 * Latency::BRANCH + 3 + 2 * Latency::DMTC1 + in GetInstructionLatency() 1503 return 2 * Latency::BRANCH + 3 + 2 * Latency::DMTC1 + in GetInstructionLatency() [all …]
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/external/llvm/lib/Target/Mips/ |
D | MipsSEInstrInfo.cpp | 161 Opc = Mips::DMTC1; in copyPhysReg() 375 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); in expandPostRAPseudo() 381 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); in expandPostRAPseudo()
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D | MipsInstrFPU.td | 387 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, 622 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64; 623 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64;
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D | MipsSEISelDAGToDAG.cpp | 755 CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero)); in trySelect()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | MipsSEInstrInfo.cpp | 166 Opc = Mips::DMTC1; in copyPhysReg() 454 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); in expandPostRAPseudo() 461 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); in expandPostRAPseudo()
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D | MipsInstrFPU.td | 515 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, 885 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64; 886 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64,
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D | MipsSEISelDAGToDAG.cpp | 810 CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero)); in trySelect()
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D | MipsSEISelLowering.cpp | 3753 ? Mips::DMTC1 in emitFPEXTEND_PSEUDO()
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/external/v8/src/compiler/mips/ |
D | instruction-scheduler-mips.cc | 410 DMTC1 = 4, enumerator
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/external/v8/src/mips64/ |
D | constants-mips64.h | 620 DMTC1 = ((0U << 3) + 5) << 21, enumerator
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D | disasm-mips64.cc | 1375 case DMTC1: in DecodeTypeRegisterCOP1()
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D | assembler-mips64.cc | 2998 GenInstrRegister(COP1, DMTC1, rt, fs, f0); in dmtc1()
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D | simulator-mips64.cc | 3584 case DMTC1: in DecodeTypeRegisterCOP1()
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/external/capstone/arch/Mips/ |
D | MipsGenAsmWriter.inc | 583 704598U, // DMTC1 2297 0U, // DMTC1 4534 // CTC1, CTC1_MM, DAHI, DATI, DMTC1, MTC1, MTC1_MM, MTHC1_MM, MTHI_DSP, M... 4585 // CTC1, CTC1_MM, DMTC1, MTC1, MTC1_MM, MTHC1_MM, MTHI_DSP, MTHLIP, MTLO_...
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D | MipsGenDisassemblerTables.inc | 819 /* 1659 */ MCD_OPC_Decode, 182, 4, 65, // Opcode: DMTC1
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
D | MipsGenMCCodeEmitter.inc | 1224 UINT64_C(1151336448), // DMTC1 6472 case Mips::DMTC1: 8950 …HasStdEnc | Feature_HasMips3 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // DMTC1 = 1211
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D | MipsGenAsmWriter.inc | 2439 8945795U, // DMTC1 5070 0U, // DMTC1
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D | MipsGenFastISel.inc | 86 return fastEmitInst_r(Mips::DMTC1, &Mips::FGR64RegClass, Op0, Op0IsKill);
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D | MipsGenDAGISel.inc | 25266 /* 46963*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMTC1), 0, 25269 // Dst: (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) 27785 /* 52218*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMTC1), 0, 27788 // Dst: (DMTC1:{ *:[f64] } ZERO_64:{ *:[i64] }) 27824 /* 52302*/ OPC_EmitNode1, TARGET_VAL(Mips::DMTC1), 0, 27829 // Dst: (FNEG_D64:{ *:[f64] } (DMTC1:{ *:[f64] } ZERO_64:{ *:[i64] }))
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D | MipsGenInstrInfo.inc | 1226 DMTC1 = 1211, 5271 …LL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1211 = DMTC1
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D | MipsGenGlobalISel.inc | 2836 …// (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) => (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] … 2837 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMTC1,
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D | MipsGenDisassemblerTables.inc | 3276 /* 2457 */ MCD::OPC_Decode, 187, 9, 199, 1, // Opcode: DMTC1
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
D | MipsAsmParser.cpp | 3420 TOut.emitRR(Mips::DMTC1, FirstReg, ATReg, IDLoc, STI); in expandLoadImmReal()
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