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Searched refs:Def (Results 1 – 25 of 378) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyLowerBrUnless.cpp78 MachineInstr *Def = MRI.getVRegDef(Cond); in runOnMachineFunction() local
79 switch (Def->getOpcode()) { in runOnMachineFunction()
81 case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break; in runOnMachineFunction()
82 case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break; in runOnMachineFunction()
83 case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break; in runOnMachineFunction()
84 case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted = true; break; in runOnMachineFunction()
85 case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted = true; break; in runOnMachineFunction()
86 case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted = true; break; in runOnMachineFunction()
87 case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted = true; break; in runOnMachineFunction()
88 case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted = true; break; in runOnMachineFunction()
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DWebAssemblyRegStackify.cpp256 static bool ShouldRematerialize(const MachineInstr &Def, AliasAnalysis &AA, in ShouldRematerialize() argument
258 return Def.isAsCheapAsAMove() && TII->isTriviallyReMaterializable(Def, &AA); in ShouldRematerialize()
269 if (MachineInstr *Def = MRI.getUniqueVRegDef(Reg)) in GetVRegDef() local
270 return Def; in GetVRegDef()
283 static bool HasOneUse(unsigned Reg, MachineInstr *Def, in HasOneUse() argument
293 LIS.getInstructionIndex(*Def).getRegSlot()); in HasOneUse()
313 static bool IsSafeToMove(const MachineInstr *Def, const MachineInstr *Insert, in IsSafeToMove() argument
315 assert(Def->getParent() == Insert->getParent()); in IsSafeToMove()
319 for (const MachineOperand &MO : Def->operands()) { in IsSafeToMove()
349 Query(*Def, AA, Read, Write, Effects, StackPointer); in IsSafeToMove()
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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyLowerBrUnless.cpp75 MachineInstr *Def = MRI.getVRegDef(Cond); in runOnMachineFunction() local
76 switch (Def->getOpcode()) { in runOnMachineFunction()
78 case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break; in runOnMachineFunction()
79 case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break; in runOnMachineFunction()
80 case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break; in runOnMachineFunction()
81 case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted = true; break; in runOnMachineFunction()
82 case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted = true; break; in runOnMachineFunction()
83 case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted = true; break; in runOnMachineFunction()
84 case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted = true; break; in runOnMachineFunction()
85 case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted = true; break; in runOnMachineFunction()
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DWebAssemblyRegStackify.cpp219 static bool ShouldRematerialize(const MachineInstr &Def, AliasAnalysis &AA, in ShouldRematerialize() argument
221 return Def.isAsCheapAsAMove() && TII->isTriviallyReMaterializable(Def, &AA); in ShouldRematerialize()
232 if (MachineInstr *Def = MRI.getUniqueVRegDef(Reg)) in GetVRegDef() local
233 return Def; in GetVRegDef()
246 static bool HasOneUse(unsigned Reg, MachineInstr *Def, in HasOneUse() argument
256 LIS.getInstructionIndex(*Def).getRegSlot()); in HasOneUse()
276 static bool IsSafeToMove(const MachineInstr *Def, const MachineInstr *Insert, in IsSafeToMove() argument
279 assert(Def->getParent() == Insert->getParent()); in IsSafeToMove()
282 for (const MachineOperand &MO : Def->operands()) { in IsSafeToMove()
312 (MO.isDef() || Def->definesRegister(Reg)) ? in IsSafeToMove()
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/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp294 const MachineInstr *Def; member in __anond69149540111::ValueTracker
354 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg), in ValueTracker()
357 Def = MRI.getVRegDef(Reg); in ValueTracker()
373 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg), in ValueTracker()
375 assert(DefIdx < Def->getDesc().getNumDefs() && in ValueTracker()
376 Def->getOperand(DefIdx).isReg() && "Invalid definition"); in ValueTracker()
377 Reg = Def->getOperand(DefIdx).getReg(); in ValueTracker()
820 TargetInstrInfo::RegSubRegPair Def, in getNewSource() argument
824 TargetInstrInfo::RegSubRegPair LookupSrc(Def.Reg, Def.SubReg); in getNewSource()
873 RewriteSource(TargetInstrInfo::RegSubRegPair Def, in RewriteSource() argument
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DMachineCopyPropagation.cpp65 bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def);
130 unsigned Def, const TargetRegisterInfo *TRI) { in isNopCopy() argument
134 assert(Def == PreviousDef); in isNopCopy()
140 return SubIdx == TRI->getSubRegIndex(PreviousDef, Def); in isNopCopy()
147 unsigned Def) { in eraseIfRedundant() argument
150 if (MRI->isReserved(Src) || MRI->isReserved(Def)) in eraseIfRedundant()
154 Reg2MIMap::iterator CI = AvailCopyMap.find(Def); in eraseIfRedundant()
160 if (!isNopCopy(PrevCopy, Src, Def, TRI)) in eraseIfRedundant()
169 assert(CopyDef == Src || CopyDef == Def); in eraseIfRedundant()
188 unsigned Def = MI->getOperand(0).getReg(); in CopyPropagateBlock() local
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DDetectDeadLanes.cpp93 LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
255 const MachineOperand &Def = MI.getOperand(0); in transferUsedLanes() local
256 unsigned DefReg = Def.getReg(); in transferUsedLanes()
290 const MachineOperand &Def = *MI.defs().begin(); in transferDefinedLanesStep() local
291 unsigned DefReg = Def.getReg(); in transferDefinedLanesStep()
301 DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes); in transferDefinedLanesStep()
313 LaneBitmask DetectDeadLanes::transferDefinedLanes(const MachineOperand &Def, in transferDefinedLanes() argument
315 const MachineInstr &MI = *Def.getParent(); in transferDefinedLanes()
349 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
351 DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg()); in transferDefinedLanes()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/WindowsManifest/
DWindowsManifestMerger.cpp128 for (xmlNsPtr Def = Node->nsDef; Def; Def = Def->next) { in search() local
129 if (Def->prefix && xmlStringsEqual(Def->href, HRef)) { in search()
130 return Def; in search()
156 if (xmlNsPtr Def = search(HRef, Node)) in searchOrDefine() local
157 return Def; in searchOrDefine()
158 if (xmlNsPtr Def = xmlNewNs(Node, HRef, getPrefixForHref(HRef))) in searchOrDefine() local
159 return Def; in searchOrDefine()
183 for (xmlNsPtr Def = Node->nsDef; Def; Def = Def->next) { in getNamespaceWithPrefix() local
184 if (xmlStringsEqual(Def->prefix, Prefix)) { in getNamespaceWithPrefix()
185 return Def; in getNamespaceWithPrefix()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp255 RegSubRegPair Def, RewriteMapTy &RewriteMap);
367 const MachineInstr *Def = nullptr; member in __anon5d64f7ac0111::ValueTracker
423 Def = MRI.getVRegDef(Reg); in ValueTracker()
1113 RegSubRegPair Def, in getNewSource() argument
1116 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg); in getNewSource()
1224 RegSubRegPair Def, RewriteMapTy &RewriteMap) { in rewriteSource() argument
1225 assert(!TargetRegisterInfo::isPhysicalRegister(Def.Reg) && in rewriteSource()
1229 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap); in rewriteSource()
1232 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource()
1240 if (Def.SubReg) { in rewriteSource()
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DDetectDeadLanes.cpp92 LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
253 const MachineOperand &Def = MI.getOperand(0); in transferUsedLanes() local
254 unsigned DefReg = Def.getReg(); in transferUsedLanes()
288 const MachineOperand &Def = *MI.defs().begin(); in transferDefinedLanesStep() local
289 unsigned DefReg = Def.getReg(); in transferDefinedLanesStep()
299 DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes); in transferDefinedLanesStep()
311 LaneBitmask DetectDeadLanes::transferDefinedLanes(const MachineOperand &Def, in transferDefinedLanes() argument
313 const MachineInstr &MI = *Def.getParent(); in transferDefinedLanes()
347 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
349 DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg()); in transferDefinedLanes()
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DMachineCopyPropagation.cpp109 bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def);
198 unsigned Def, const TargetRegisterInfo *TRI) { in isNopCopy() argument
202 assert(Def == PreviousDef); in isNopCopy()
208 return SubIdx == TRI->getSubRegIndex(PreviousDef, Def); in isNopCopy()
215 unsigned Def) { in eraseIfRedundant() argument
218 if (MRI->isReserved(Src) || MRI->isReserved(Def)) in eraseIfRedundant()
222 Reg2MIMap::iterator CI = AvailCopyMap.find(Def); in eraseIfRedundant()
230 if (!isNopCopy(PrevCopy, Src, Def, TRI)) in eraseIfRedundant()
239 assert(CopyDef == Src || CopyDef == Def); in eraseIfRedundant()
407 unsigned Def = MI->getOperand(0).getReg(); in CopyPropagateBlock() local
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/external/llvm/lib/Target/AArch64/
DAArch64CollectLOH.cpp501 static bool canDefBePartOfLOH(const MachineInstr *Def) { in canDefBePartOfLOH() argument
502 unsigned Opc = Def->getOpcode(); in canDefBePartOfLOH()
511 switch (Def->getOperand(2).getType()) { in canDefBePartOfLOH()
522 switch (Def->getOperand(2).getType()) { in canDefBePartOfLOH()
578 const MachineInstr *Def = DefsIt.first; in reachedUsesToDefs() local
582 if ((ADRPMode && Def->getOpcode() != AArch64::ADRP) || in reachedUsesToDefs()
583 (!ADRPMode && !canDefBePartOfLOH(Def)) || in reachedUsesToDefs()
701 const MachineInstr *Def = *UseToDefs.find(Instr)->second.begin(); in isCandidate() local
702 if (Def->getOpcode() != AArch64::ADRP) { in isCandidate()
709 if (!MDT->dominates(Def, Instr)) in isCandidate()
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DAArch64AdvSIMDScalarPass.cpp217 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform() local
219 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
220 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in isProfitableToTransform()
230 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform() local
232 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
233 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
310 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction() local
312 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in transformInstruction()
313 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in transformInstruction()
323 Def->eraseFromParent(); in transformInstruction()
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/external/llvm/lib/IR/
DDominators.cpp75 bool DominatorTree::dominates(const Instruction *Def, in dominates() argument
78 const BasicBlock *DefBB = Def->getParent(); in dominates()
89 if (Def == User) in dominates()
96 if (isa<InvokeInst>(Def) || isa<PHINode>(User)) in dominates()
97 return dominates(Def, UseBB); in dominates()
104 for (; &*I != Def && &*I != User; ++I) in dominates()
107 return &*I == Def; in dominates()
112 bool DominatorTree::dominates(const Instruction *Def, in dominates() argument
114 const BasicBlock *DefBB = Def->getParent(); in dominates()
129 if (const auto *II = dyn_cast<InvokeInst>(Def)) { in dominates()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/ToolDrivers/llvm-dlltool/
DDlltoolDriver.cpp137 Expected<COFFModuleDefinition> Def = in dlltoolDriverMain() local
140 if (!Def) { in dlltoolDriverMain()
142 << errorToErrorCode(Def.takeError()).message(); in dlltoolDriverMain()
148 Def->OutputFile = Arg->getValue(); in dlltoolDriverMain()
150 if (Def->OutputFile.empty()) { in dlltoolDriverMain()
157 Path = getImplibPath(Def->OutputFile); in dlltoolDriverMain()
160 for (COFFShortExport& E : Def->Exports) { in dlltoolDriverMain()
176 if (writeImportLibrary(Def->OutputFile, Path, Def->Exports, Machine, true)) in dlltoolDriverMain()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp210 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform() local
212 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
213 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in isProfitableToTransform()
223 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform() local
225 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
226 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
303 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction() local
305 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in transformInstruction()
306 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in transformInstruction()
316 Def->eraseFromParent(); in transformInstruction()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86WinAllocaExpander.cpp86 MachineInstr *Def = MRI->getUniqueVRegDef(AmountReg); in getWinAllocaAmount() local
89 while (Def && Def->isCopy() && Def->getOperand(1).isReg()) in getWinAllocaAmount()
90 Def = MRI->getUniqueVRegDef(Def->getOperand(1).getReg()); in getWinAllocaAmount()
92 if (!Def || in getWinAllocaAmount()
93 (Def->getOpcode() != X86::MOV32ri && Def->getOpcode() != X86::MOV64ri) || in getWinAllocaAmount()
94 !Def->getOperand(1).isImm()) in getWinAllocaAmount()
97 return Def->getOperand(1).getImm(); in getWinAllocaAmount()
/external/llvm/lib/Target/X86/
DX86WinAllocaExpander.cpp85 MachineInstr *Def = MRI->getUniqueVRegDef(AmountReg); in getWinAllocaAmount() local
88 while (Def && Def->isCopy() && Def->getOperand(1).isReg()) in getWinAllocaAmount()
89 Def = MRI->getUniqueVRegDef(Def->getOperand(1).getReg()); in getWinAllocaAmount()
91 if (!Def || in getWinAllocaAmount()
92 (Def->getOpcode() != X86::MOV32ri && Def->getOpcode() != X86::MOV64ri) || in getWinAllocaAmount()
93 !Def->getOperand(1).isImm()) in getWinAllocaAmount()
96 return Def->getOperand(1).getImm(); in getWinAllocaAmount()
/external/llvm/utils/TableGen/
DCodeGenSchedule.h61 CodeGenSchedRW(unsigned Idx, Record *Def) in CodeGenSchedRW()
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) { in CodeGenSchedRW()
63 Name = Def->getName(); in CodeGenSchedRW()
64 IsRead = Def->isSubClassOf("SchedRead"); in CodeGenSchedRW()
65 HasVariants = Def->isSubClassOf("SchedVariant"); in CodeGenSchedRW()
67 IsVariadic = Def->getValueAsBit("Variadic"); in CodeGenSchedRW()
72 IsSequence = Def->isSubClassOf("WriteSequence"); in CodeGenSchedRW()
333 CodeGenSchedRW &getSchedRW(Record *Def) { in getSchedRW() argument
334 bool IsRead = Def->isSubClassOf("SchedRead"); in getSchedRW()
335 unsigned Idx = getSchedRWIdx(Def, IsRead); in getSchedRW()
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/external/clang/test/Index/Core/
Dindex-source.m11 // CHECK: [[@LINE+1]]:6 | function/C | goo | c:@F@goo | _goo | Def | rel: 0
52 // CHECK: [[@LINE+1]]:6 | enum/C | MyEnum | c:@E@MyEnum | <no-cgname> | Def | rel: 0
54 …merator/C | EnumeratorInNamed | c:@E@MyEnum@EnumeratorInNamed | <no-cgname> | Def,RelChild | rel: 1
59 // CHECK: [[@LINE+1]]:1 | enum/C | <no-name> | c:@Ea@One | <no-cgname> | Def | rel: 0
61 // CHECK: [[@LINE+2]]:3 | enumerator/C | One | c:@Ea@One@One | <no-cgname> | Def,RelChild | rel: 1
64 // CHECK: [[@LINE+2]]:3 | enumerator/C | Two | c:@Ea@One@Two | <no-cgname> | Def,RelChild | rel: 1
69 // CHECK: [[@LINE+1]]:13 | type-alias/C | jmp_buf | c:index-source.m@T@jmp_buf | <no-cgname> | Def …
85 // CHECK: [[@LINE+2]]:17 | field/ObjC | _prop | c:objc(cs)I2@_prop | <no-cgname> | Def,Impl,RelChil…
89 // CHECK: [[@LINE+4]]:13 | instance-method/ObjC | prop | c:objc(cs)I2(im)prop | -[I2 prop] | Def,Re…
91 …instance-method/ObjC | setProp: | c:objc(cs)I2(im)setProp: | -[I2 setProp:] | Def,RelChild | rel: 1
[all …]
Dindex-subkinds.m10 // CHECK: [[@LINE+1]]:17 | class(test)/ObjC | MyTestCase | c:objc(cs)MyTestCase | <no-cgname> | Def…
12 …t)/ObjC | testMe | c:objc(cs)MyTestCase(im)testMe | -[MyTestCase testMe] | Def,Dyn,RelChild | rel:…
14 …stResult | c:objc(cs)MyTestCase(im)testResult | -[MyTestCase testResult] | Def,Dyn,RelChild | rel:…
16 …Int: | c:objc(cs)MyTestCase(im)testWithInt: | -[MyTestCase testWithInt:] | Def,Dyn,RelChild | rel:…
23 …[@LINE+1]]:17 | class(test)/ObjC | SubTestCase | c:objc(cs)SubTestCase | <no-cgname> | Def | rel: 0
25 …jC | testIt2 | c:objc(cs)SubTestCase(im)testIt2 | -[SubTestCase testIt2] | Def,Dyn,RelChild | rel:…
32 …[@LINE+1]]:17 | extension/ObjC | MyTestCase | c:objc(cy)MyTestCase@cat | <no-cgname> | Def | rel: 0
34 …InCat | c:objc(cs)MyTestCase(im)testInCat | -[MyTestCase(cat) testInCat] | Def,Dyn,RelChild | rel:…
/external/lzma/CPP/Common/
DMyTypes.h13 bool Def; member
15 CBoolPair(): Val(false), Def(false) {} in CBoolPair()
20 Def = false; in Init()
26 Def = true; in SetTrueTrue()
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-pdbutil/
DMinimalSymbolDumper.cpp536 CVSymbol &CVR, DefRangeFramePointerRelFullScopeSym &Def) { in visitKnownRecord() argument
537 P.format(" offset = {0}", Def.Offset); in visitKnownRecord()
542 DefRangeFramePointerRelSym &Def) { in visitKnownRecord() argument
544 P.formatLine("offset = {0}, range = {1}", Def.Offset, formatRange(Def.Range)); in visitKnownRecord()
545 P.formatLine("gaps = {2}", Def.Offset, in visitKnownRecord()
546 formatGaps(P.getIndentLevel() + 9, Def.Gaps)); in visitKnownRecord()
551 DefRangeRegisterRelSym &Def) { in visitKnownRecord() argument
555 uint16_t(Def.Hdr.Register), int32_t(Def.Hdr.BasePointerOffset), in visitKnownRecord()
556 Def.offsetInParent(), Def.hasSpilledUDTMember()); in visitKnownRecord()
557 P.formatLine("range = {0}, gaps = {1}", formatRange(Def.Range), in visitKnownRecord()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/
DDominators.cpp111 bool DominatorTree::dominates(const Instruction *Def, in dominates() argument
114 const BasicBlock *DefBB = Def->getParent(); in dominates()
125 if (Def == User) in dominates()
132 if (isa<InvokeInst>(Def) || isa<PHINode>(User)) in dominates()
133 return dominates(Def, UseBB); in dominates()
140 for (; &*I != Def && &*I != User; ++I) in dominates()
143 return &*I == Def; in dominates()
148 bool DominatorTree::dominates(const Instruction *Def, in dominates() argument
150 const BasicBlock *DefBB = Def->getParent(); in dominates()
165 if (const auto *II = dyn_cast<InvokeInst>(Def)) { in dominates()
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/external/clang/lib/Lex/
DMacroInfo.cpp202 for (DefInfo Def = getDefinition(); Def; Def = Def.getPreviousDefinition()) { in findDirectiveAtLoc() local
203 if (Def.getLocation().isInvalid() || // For macros defined on the command line. in findDirectiveAtLoc()
204 SM.isBeforeInTranslationUnit(Def.getLocation(), L)) in findDirectiveAtLoc()
205 return (!Def.isUndefined() || in findDirectiveAtLoc()
206 SM.isBeforeInTranslationUnit(L, Def.getUndefLocation())) in findDirectiveAtLoc()
207 ? Def : DefInfo(); in findDirectiveAtLoc()

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