| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPURegisterInfo.td | 24 def R0 : SPUVecReg<0, "$lr">, DwarfRegNum<[0]>;
25 def R1 : SPUVecReg<1, "$sp">, DwarfRegNum<[1]>;
26 def R2 : SPUVecReg<2, "$2">, DwarfRegNum<[2]>;
27 def R3 : SPUVecReg<3, "$3">, DwarfRegNum<[3]>;
28 def R4 : SPUVecReg<4, "$4">, DwarfRegNum<[4]>;
29 def R5 : SPUVecReg<5, "$5">, DwarfRegNum<[5]>;
30 def R6 : SPUVecReg<6, "$6">, DwarfRegNum<[6]>;
31 def R7 : SPUVecReg<7, "$7">, DwarfRegNum<[7]>;
32 def R8 : SPUVecReg<8, "$8">, DwarfRegNum<[8]>;
33 def R9 : SPUVecReg<9, "$9">, DwarfRegNum<[9]>;
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 52 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
53 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
54 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
55 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
56 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
57 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
58 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
59 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
60 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
61 def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>;
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 68 def R0 : GPR< 0, "r0">, DwarfRegNum<[-2, 0]>;
69 def R1 : GPR< 1, "r1">, DwarfRegNum<[-2, 1]>;
70 def R2 : GPR< 2, "r2">, DwarfRegNum<[-2, 2]>;
71 def R3 : GPR< 3, "r3">, DwarfRegNum<[-2, 3]>;
72 def R4 : GPR< 4, "r4">, DwarfRegNum<[-2, 4]>;
73 def R5 : GPR< 5, "r5">, DwarfRegNum<[-2, 5]>;
74 def R6 : GPR< 6, "r6">, DwarfRegNum<[-2, 6]>;
75 def R7 : GPR< 7, "r7">, DwarfRegNum<[-2, 7]>;
76 def R8 : GPR< 8, "r8">, DwarfRegNum<[-2, 8]>;
77 def R9 : GPR< 9, "r9">, DwarfRegNum<[-2, 9]>;
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaRegisterInfo.td | 38 def R0 : GPR< 0, "$0">, DwarfRegNum<[0]>;
39 def R1 : GPR< 1, "$1">, DwarfRegNum<[1]>;
40 def R2 : GPR< 2, "$2">, DwarfRegNum<[2]>;
41 def R3 : GPR< 3, "$3">, DwarfRegNum<[3]>;
42 def R4 : GPR< 4, "$4">, DwarfRegNum<[4]>;
43 def R5 : GPR< 5, "$5">, DwarfRegNum<[5]>;
44 def R6 : GPR< 6, "$6">, DwarfRegNum<[6]>;
45 def R7 : GPR< 7, "$7">, DwarfRegNum<[7]>;
46 def R8 : GPR< 8, "$8">, DwarfRegNum<[8]>;
47 def R9 : GPR< 9, "$9">, DwarfRegNum<[9]>;
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.td | 42 def R0 : MBlazeGPRReg< 0, "r0">, DwarfRegNum<[0]>;
43 def R1 : MBlazeGPRReg< 1, "r1">, DwarfRegNum<[1]>;
44 def R2 : MBlazeGPRReg< 2, "r2">, DwarfRegNum<[2]>;
45 def R3 : MBlazeGPRReg< 3, "r3">, DwarfRegNum<[3]>;
46 def R4 : MBlazeGPRReg< 4, "r4">, DwarfRegNum<[4]>;
47 def R5 : MBlazeGPRReg< 5, "r5">, DwarfRegNum<[5]>;
48 def R6 : MBlazeGPRReg< 6, "r6">, DwarfRegNum<[6]>;
49 def R7 : MBlazeGPRReg< 7, "r7">, DwarfRegNum<[7]>;
50 def R8 : MBlazeGPRReg< 8, "r8">, DwarfRegNum<[8]>;
51 def R9 : MBlazeGPRReg< 9, "r9">, DwarfRegNum<[9]>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 89 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>;
92 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
93 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
94 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
98 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
99 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
100 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
101 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
102 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
103 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.td | 29 def R0 : Core< 0, "%r0">, DwarfRegNum<[0]>;
30 def R1 : Core< 1, "%r1">, DwarfRegNum<[1]>;
31 def R2 : Core< 2, "%r2">, DwarfRegNum<[2]>;
32 def R3 : Core< 3, "%r3">, DwarfRegNum<[3]>;
34 def R4 : Core< 4, "%r4">, DwarfRegNum<[4]>;
35 def R5 : Core< 5, "%r5">, DwarfRegNum<[5]>;
36 def R6 : Core< 6, "%r6">, DwarfRegNum<[6]>;
37 def R7 : Core< 7, "%r7">, DwarfRegNum<[7]>;
38 def R8 : Core< 8, "%r8">, DwarfRegNum<[8]>;
39 def R9 : Core< 9, "%r9">, DwarfRegNum<[9]>;
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVRegisterInfo.td | 49 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
51 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
52 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
53 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
54 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
55 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
56 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
57 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
59 def X8 : RISCVReg<8, "x8", ["s0"]>, DwarfRegNum<[8]>;
60 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 90 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>;
93 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
94 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
95 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
99 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
100 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
101 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
102 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
103 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
104 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 45 def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>;
46 def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>;
47 def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>;
48 def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>;
49 def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>;
50 def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
51 def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
52 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
53 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
54 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
[all …]
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| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 45 def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>;
46 def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>;
47 def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>;
48 def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>;
49 def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>;
50 def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
51 def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
52 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
53 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
54 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 71 // FIXME: Fix DwarfRegNum.
74 def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
75 def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
76 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
77 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
78 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
79 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
80 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
81 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
82 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 72 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
128 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
129 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
130 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
131 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
132 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
133 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
134 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
135 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
136 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 72 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
128 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
129 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
130 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
131 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
132 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
133 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
134 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
135 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
136 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinRegisterInfo.td | 76 def CC : Rc<5, "cc">, DwarfRegNum<[34]>;
91 def R0 : Rii<0, 0, "r0", [R0H, R0L]>, DwarfRegNum<[0]>;
93 def R1 : Rii<0, 1, "r1", [R1H, R1L]>, DwarfRegNum<[1]>;
95 def R2 : Rii<0, 2, "r2", [R2H, R2L]>, DwarfRegNum<[2]>;
97 def R3 : Rii<0, 3, "r3", [R3H, R3L]>, DwarfRegNum<[3]>;
99 def R4 : Rii<0, 4, "r4", [R4H, R4L]>, DwarfRegNum<[4]>;
101 def R5 : Rii<0, 5, "r5", [R5H, R5L]>, DwarfRegNum<[5]>;
103 def R6 : Rii<0, 6, "r6", [R6H, R6L]>, DwarfRegNum<[6]>;
105 def R7 : Rii<0, 7, "r7", [R7H, R7L]>, DwarfRegNum<[7]>;
109 def P0 : Rii<1, 0, "p0", [P0H, P0L]>, DwarfRegNum<[8]>;
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| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 26 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
27 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
28 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
29 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
30 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
31 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
32 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
33 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
34 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
35 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
89 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
91 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
92 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
93 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
94 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
95 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
96 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
97 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 26 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
27 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
28 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
29 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
30 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
31 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
32 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
33 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
34 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
35 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 26 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
27 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
28 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
29 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
30 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
31 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
32 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
33 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
34 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
35 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
89 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
91 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
92 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
93 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
94 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
95 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
96 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
97 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 82 def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>;
83 def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>;
84 def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>;
85 def R3D : GPR64< 3, "r3", [R3W]>, DwarfRegNum<[3]>;
86 def R4D : GPR64< 4, "r4", [R4W]>, DwarfRegNum<[4]>;
87 def R5D : GPR64< 5, "r5", [R5W]>, DwarfRegNum<[5]>;
88 def R6D : GPR64< 6, "r6", [R6W]>, DwarfRegNum<[6]>;
89 def R7D : GPR64< 7, "r7", [R7W]>, DwarfRegNum<[7]>;
90 def R8D : GPR64< 8, "r8", [R8W]>, DwarfRegNum<[8]>;
91 def R9D : GPR64< 9, "r9", [R9W]>, DwarfRegNum<[9]>;
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 105 def EAX : X86Reg<"eax", 0, [AX]>, DwarfRegNum<[-2, 0, 0]>;
106 def EDX : X86Reg<"edx", 2, [DX]>, DwarfRegNum<[-2, 2, 2]>;
107 def ECX : X86Reg<"ecx", 1, [CX]>, DwarfRegNum<[-2, 1, 1]>;
108 def EBX : X86Reg<"ebx", 3, [BX]>, DwarfRegNum<[-2, 3, 3]>;
109 def ESI : X86Reg<"esi", 6, [SI]>, DwarfRegNum<[-2, 6, 6]>;
110 def EDI : X86Reg<"edi", 7, [DI]>, DwarfRegNum<[-2, 7, 7]>;
111 def EBP : X86Reg<"ebp", 5, [BP]>, DwarfRegNum<[-2, 4, 5]>;
112 def ESP : X86Reg<"esp", 4, [SP]>, DwarfRegNum<[-2, 5, 4]>;
113 def EIP : X86Reg<"eip", 0, [IP]>, DwarfRegNum<[-2, 8, 8]>;
129 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
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| /external/llvm/lib/Target/BPF/ |
| D | BPFRegisterInfo.td | 22 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
23 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
24 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
25 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
26 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
27 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
28 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
29 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
30 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
31 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/ |
| D | Nios2RegisterInfo.td | 27 def ZERO : Nios2GPRReg<0, "zero">, DwarfRegNum<[ 0 ]>;
28 def AT : Nios2GPRReg<1, "at">, DwarfRegNum<[ 1 ]>;
30 def R #RegNum : Nios2GPRReg<RegNum, "r" #RegNum>, DwarfRegNum<[ RegNum ]>;
32 def ET : Nios2GPRReg<24, "et">, DwarfRegNum<[ 24 ]>;
33 def BT : Nios2GPRReg<25, "bt">, DwarfRegNum<[ 25 ]>;
34 def GP : Nios2GPRReg<26, "gp">, DwarfRegNum<[ 26 ]>;
35 def SP : Nios2GPRReg<27, "sp">, DwarfRegNum<[ 27 ]>;
36 def FP : Nios2GPRReg<28, "fp">, DwarfRegNum<[ 28 ]>;
37 def EA : Nios2GPRReg<29, "ea">, DwarfRegNum<[ 29 ]>;
38 def BA : Nios2GPRReg<30, "ba">, DwarfRegNum<[ 30 ]>;
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 142 def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>;
143 def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>;
144 def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>;
145 def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>;
146 def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>;
147 def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>;
148 def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>;
149 def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>;
150 def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>;
168 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
[all …]
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