1//===- MBlazeRegisterInfo.td - MBlaze Register defs --------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the MicroBlaze register file 12//===----------------------------------------------------------------------===// 13 14// We have banks of 32 registers each. 15class MBlazeReg<string n> : Register<n> { 16 field bits<5> Num; 17 let Namespace = "MBlaze"; 18} 19 20// Special purpose registers have 15-bit values 21class MBlazeSReg<string n> : Register<n> { 22 field bits<15> Num; 23 let Namespace = "MBlaze"; 24} 25 26// MBlaze general purpose registers 27class MBlazeGPRReg<bits<5> num, string n> : MBlazeReg<n> { 28 let Num = num; 29} 30 31// MBlaze special purpose registers 32class MBlazeSPRReg<bits<15> num, string n> : MBlazeSReg<n> { 33 let Num = num; 34} 35 36//===----------------------------------------------------------------------===// 37// Registers 38//===----------------------------------------------------------------------===// 39 40let Namespace = "MBlaze" in { 41 // General Purpose Registers 42 def R0 : MBlazeGPRReg< 0, "r0">, DwarfRegNum<[0]>; 43 def R1 : MBlazeGPRReg< 1, "r1">, DwarfRegNum<[1]>; 44 def R2 : MBlazeGPRReg< 2, "r2">, DwarfRegNum<[2]>; 45 def R3 : MBlazeGPRReg< 3, "r3">, DwarfRegNum<[3]>; 46 def R4 : MBlazeGPRReg< 4, "r4">, DwarfRegNum<[4]>; 47 def R5 : MBlazeGPRReg< 5, "r5">, DwarfRegNum<[5]>; 48 def R6 : MBlazeGPRReg< 6, "r6">, DwarfRegNum<[6]>; 49 def R7 : MBlazeGPRReg< 7, "r7">, DwarfRegNum<[7]>; 50 def R8 : MBlazeGPRReg< 8, "r8">, DwarfRegNum<[8]>; 51 def R9 : MBlazeGPRReg< 9, "r9">, DwarfRegNum<[9]>; 52 def R10 : MBlazeGPRReg< 10, "r10">, DwarfRegNum<[10]>; 53 def R11 : MBlazeGPRReg< 11, "r11">, DwarfRegNum<[11]>; 54 def R12 : MBlazeGPRReg< 12, "r12">, DwarfRegNum<[12]>; 55 def R13 : MBlazeGPRReg< 13, "r13">, DwarfRegNum<[13]>; 56 def R14 : MBlazeGPRReg< 14, "r14">, DwarfRegNum<[14]>; 57 def R15 : MBlazeGPRReg< 15, "r15">, DwarfRegNum<[15]>; 58 def R16 : MBlazeGPRReg< 16, "r16">, DwarfRegNum<[16]>; 59 def R17 : MBlazeGPRReg< 17, "r17">, DwarfRegNum<[17]>; 60 def R18 : MBlazeGPRReg< 18, "r18">, DwarfRegNum<[18]>; 61 def R19 : MBlazeGPRReg< 19, "r19">, DwarfRegNum<[19]>; 62 def R20 : MBlazeGPRReg< 20, "r20">, DwarfRegNum<[20]>; 63 def R21 : MBlazeGPRReg< 21, "r21">, DwarfRegNum<[21]>; 64 def R22 : MBlazeGPRReg< 22, "r22">, DwarfRegNum<[22]>; 65 def R23 : MBlazeGPRReg< 23, "r23">, DwarfRegNum<[23]>; 66 def R24 : MBlazeGPRReg< 24, "r24">, DwarfRegNum<[24]>; 67 def R25 : MBlazeGPRReg< 25, "r25">, DwarfRegNum<[25]>; 68 def R26 : MBlazeGPRReg< 26, "r26">, DwarfRegNum<[26]>; 69 def R27 : MBlazeGPRReg< 27, "r27">, DwarfRegNum<[27]>; 70 def R28 : MBlazeGPRReg< 28, "r28">, DwarfRegNum<[28]>; 71 def R29 : MBlazeGPRReg< 29, "r29">, DwarfRegNum<[29]>; 72 def R30 : MBlazeGPRReg< 30, "r30">, DwarfRegNum<[30]>; 73 def R31 : MBlazeGPRReg< 31, "r31">, DwarfRegNum<[31]>; 74 75 // Special Purpose Registers 76 def RPC : MBlazeSPRReg<0x0000, "rpc">, DwarfRegNum<[32]>; 77 def RMSR : MBlazeSPRReg<0x0001, "rmsr">, DwarfRegNum<[33]>; 78 def REAR : MBlazeSPRReg<0x0003, "rear">, DwarfRegNum<[34]>; 79 def RESR : MBlazeSPRReg<0x0005, "resr">, DwarfRegNum<[35]>; 80 def RFSR : MBlazeSPRReg<0x0007, "rfsr">, DwarfRegNum<[36]>; 81 def RBTR : MBlazeSPRReg<0x000B, "rbtr">, DwarfRegNum<[37]>; 82 def REDR : MBlazeSPRReg<0x000D, "redr">, DwarfRegNum<[38]>; 83 def RPID : MBlazeSPRReg<0x1000, "rpid">, DwarfRegNum<[39]>; 84 def RZPR : MBlazeSPRReg<0x1001, "rzpr">, DwarfRegNum<[40]>; 85 def RTLBX : MBlazeSPRReg<0x1002, "rtlbx">, DwarfRegNum<[41]>; 86 def RTLBLO : MBlazeSPRReg<0x1003, "rtlblo">, DwarfRegNum<[42]>; 87 def RTLBHI : MBlazeSPRReg<0x1004, "rtlbhi">, DwarfRegNum<[43]>; 88 def RTLBSX : MBlazeSPRReg<0x1004, "rtlbsx">, DwarfRegNum<[44]>; 89 def RPVR0 : MBlazeSPRReg<0x2000, "rpvr0">, DwarfRegNum<[45]>; 90 def RPVR1 : MBlazeSPRReg<0x2001, "rpvr1">, DwarfRegNum<[46]>; 91 def RPVR2 : MBlazeSPRReg<0x2002, "rpvr2">, DwarfRegNum<[47]>; 92 def RPVR3 : MBlazeSPRReg<0x2003, "rpvr3">, DwarfRegNum<[48]>; 93 def RPVR4 : MBlazeSPRReg<0x2004, "rpvr4">, DwarfRegNum<[49]>; 94 def RPVR5 : MBlazeSPRReg<0x2005, "rpvr5">, DwarfRegNum<[50]>; 95 def RPVR6 : MBlazeSPRReg<0x2006, "rpvr6">, DwarfRegNum<[51]>; 96 def RPVR7 : MBlazeSPRReg<0x2007, "rpvr7">, DwarfRegNum<[52]>; 97 def RPVR8 : MBlazeSPRReg<0x2008, "rpvr8">, DwarfRegNum<[53]>; 98 def RPVR9 : MBlazeSPRReg<0x2009, "rpvr9">, DwarfRegNum<[54]>; 99 def RPVR10 : MBlazeSPRReg<0x200A, "rpvr10">, DwarfRegNum<[55]>; 100 def RPVR11 : MBlazeSPRReg<0x200B, "rpvr11">, DwarfRegNum<[56]>; 101 102 // The carry bit. In the Microblaze this is really bit 29 of the 103 // MSR register but this is the only bit of that register that we 104 // are interested in modeling. 105 def CARRY : MBlazeSPRReg<0x0000, "rmsr[c]">; 106} 107 108//===----------------------------------------------------------------------===// 109// Register Classes 110//===----------------------------------------------------------------------===// 111 112def GPR : RegisterClass<"MBlaze", [i32,f32], 32, (sequence "R%u", 0, 31)>; 113 114def SPR : RegisterClass<"MBlaze", [i32], 32, (add 115 // Reserved 116 RPC, 117 RMSR, 118 REAR, 119 RESR, 120 RFSR, 121 RBTR, 122 REDR, 123 RPID, 124 RZPR, 125 RTLBX, 126 RTLBLO, 127 RTLBHI, 128 RPVR0, 129 RPVR1, 130 RPVR2, 131 RPVR3, 132 RPVR4, 133 RPVR5, 134 RPVR6, 135 RPVR7, 136 RPVR8, 137 RPVR9, 138 RPVR10, 139 RPVR11 140 )> 141{ 142 // None of the special purpose registers are allocatable. 143 let isAllocatable = 0; 144} 145 146def CRC : RegisterClass<"MBlaze", [i32], 32, (add CARRY)> { 147 let CopyCost = -1; 148} 149