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Searched refs:EBI_BASE (Results 1 – 10 of 10) sorted by relevance

/external/u-boot/board/micronas/vct/
Debi_onenand.c16 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr)); in ebi_nand_read_word()
19 return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)) >> 16; in ebi_nand_read_word()
25 reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16)); in ebi_nand_write_word()
26 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), in ebi_nand_write_word()
36 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); in ebi_init_onenand()
38 reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002); in ebi_init_onenand()
39 reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); in ebi_init_onenand()
41 reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002); in ebi_init_onenand()
42 reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */ in ebi_init_onenand()
44 reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000); in ebi_init_onenand()
[all …]
Debi_smc911x.c16 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x00003020); in ebi_init_smc911x()
17 reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); in ebi_init_smc911x()
19 reg_write(EBI_DEV1_TIM1_RD1(EBI_BASE), 0x00501100); in ebi_init_smc911x()
20 reg_write(EBI_DEV1_TIM1_RD2(EBI_BASE), 0x0FF02111); in ebi_init_smc911x()
22 reg_write(EBI_DEV1_TIM_EXT(EBI_BASE), 0xFFF00000); in ebi_init_smc911x()
23 reg_write(EBI_DEV1_EXT_ACC(EBI_BASE), 0x0FFFFFFF); in ebi_init_smc911x()
25 reg_write(EBI_DEV1_TIM1_WR1(EBI_BASE), 0x05001100); in ebi_init_smc911x()
26 reg_write(EBI_DEV1_TIM1_WR2(EBI_BASE), 0x3FC21110); in ebi_init_smc911x()
40 reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); in smc911x_reg_read()
42 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr)); in smc911x_reg_read()
[all …]
Debi_nor_flash.c14 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), EXT_DEVICE_CHANNEL_2 | addr); in ebi_read()
17 return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); in ebi_read()
28 reg_write(EBI_IO_ACCS_DATA(EBI_BASE), val); in ebi_write_u16()
29 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), in ebi_write_u16()
35 while (!(reg_read(EBI_SIG_LEVEL(EBI_BASE)) & EXT_CPU_IORDY_SL)) { in ebi_write_u16()
64 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); in ebi_init_nor_flash()
66 reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x400002); in ebi_init_nor_flash()
67 reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); in ebi_init_nor_flash()
69 reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x409113); in ebi_init_nor_flash()
70 reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0xFF01000); in ebi_init_nor_flash()
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Debi.c29 reg_write(EBI_CTRL_SIG_ACTLV(EBI_BASE), 0x00004100); in ebi_initialize()
Debi.h77 while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE) in ebi_wait()
/external/u-boot/board/armltd/integrator/
Dintegrator.c97 writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG); in board_init()
98 val = readl(EBI_BASE + EBI_CSR1_REG); in board_init()
101 writel(val, EBI_BASE + EBI_CSR1_REG); in board_init()
102 writel(0, EBI_BASE + EBI_LOCK_REG); in board_init()
Darm-ebi.h13 #define EBI_BASE 0x12000000 macro
/external/u-boot/board/micronas/vct/vcth/
Dreg_ebi.h11 #define EBI_BASE 0x00000000 macro
/external/u-boot/board/micronas/vct/vcth2/
Dreg_ebi.h11 #define EBI_BASE 0x00000000 macro
/external/u-boot/board/micronas/vct/vctv/
Dreg_ebi.h11 #define EBI_BASE 0x00014000 macro