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Searched refs:ESDCTL_DDR2_OCD_DEFAULT (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/cpu/arm1136/mx35/
Dmx35_sdram.c18 #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 macro
108 writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT); in mx3_setup_sdram_bank()
/external/u-boot/board/freescale/mx35pdk/
Dmx35pdk.h38 #define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 macro
Dlowlevel_init.S216 ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT