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1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 *
5 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
6 */
7
8#include <config.h>
9#include <asm/arch/imx-regs.h>
10#include <generated/asm-offsets.h>
11#include "mx35pdk.h"
12#include <asm/arch/lowlevel_macro.S>
13
14/*
15 * return soc version
16 * 	0x10:  TO1
17 *	0x20:  TO2
18 *	0x30:  TO3
19 */
20.macro check_soc_version ret, tmp
21	ldr \tmp, =IIM_BASE_ADDR
22	ldr \ret, [\tmp, #IIM_SREV]
23	cmp \ret, #0x00
24	moveq \tmp, #ROMPATCH_REV
25	ldreq \ret, [\tmp]
26	moveq \ret, \ret, lsl #4
27	addne \ret, \ret, #0x10
28.endm
29
30/* CPLD on CS5 setup */
31.macro init_debug_board
32	ldr r0, =DBG_BASE_ADDR
33	ldr r1, =DBG_CSCR_U_CONFIG
34	str r1, [r0, #0x00]
35	ldr r1, =DBG_CSCR_L_CONFIG
36	str r1, [r0, #0x04]
37	ldr r1, =DBG_CSCR_A_CONFIG
38	str r1, [r0, #0x08]
39.endm
40
41/* clock setup */
42.macro init_clock
43	ldr r0, =CCM_BASE_ADDR
44
45	/* default CLKO to 1/32 of the ARM core*/
46	ldr r1, [r0, #CLKCTL_COSR]
47	bic r1, r1, #0x00000FF00
48	bic r1, r1, #0x0000000FF
49	mov r2, #0x00006C00
50	add r2, r2, #0x67
51	orr r1, r1, r2
52	str r1, [r0, #CLKCTL_COSR]
53
54	ldr r2, =CCM_CCMR_CONFIG
55	str r2, [r0, #CLKCTL_CCMR]
56
57	check_soc_version r1, r2
58	cmp r1, #CHIP_REV_2_0
59	ldrhs r3, =CCM_MPLL_532_HZ
60	bhs 1f
61	ldr r2, [r0, #CLKCTL_PDR0]
62	tst r2, #CLKMODE_CONSUMER
63	ldrne r3, =CCM_MPLL_532_HZ  /* consumer path*/
64	ldreq r3, =CCM_MPLL_399_HZ  /* auto path*/
651:
66	str r3, [r0, #CLKCTL_MPCTL]
67
68	ldr r1, =CCM_PPLL_300_HZ
69	str r1, [r0, #CLKCTL_PPCTL]
70
71	ldr r1, =CCM_PDR0_CONFIG
72	bic r1, r1, #0x800000
73	str r1, [r0, #CLKCTL_PDR0]
74
75	ldr r1, [r0, #CLKCTL_CGR0]
76	orr r1, r1, #0x0C300000
77	str r1, [r0, #CLKCTL_CGR0]
78
79	ldr r1, [r0, #CLKCTL_CGR1]
80	orr r1, r1, #0x00000C00
81	orr r1, r1, #0x00000003
82	str r1, [r0, #CLKCTL_CGR1]
83
84	ldr r1, [r0, #CLKCTL_CGR2]
85	orr r1, r1, #0x00C00000
86	str r1, [r0, #CLKCTL_CGR2]
87.endm
88
89.macro setup_sdram
90	ldr r0, =ESDCTL_BASE_ADDR
91	mov r3, #0x2000
92	str r3, [r0, #0x0]
93	str r3, [r0, #0x8]
94
95	/*ip(r12) has used to save lr register in upper calling*/
96	mov fp, lr
97
98	mov r5, #0x00
99	mov r2, #0x00
100	mov r1, #CSD0_BASE_ADDR
101	bl setup_sdram_bank
102
103	mov r5, #0x00
104	mov r2, #0x00
105	mov r1, #CSD1_BASE_ADDR
106	bl setup_sdram_bank
107
108	mov lr, fp
109
1101:
111	ldr r3, =ESDCTL_DELAY_LINE5
112	str r3, [r0, #0x30]
113.endm
114
115.globl lowlevel_init
116lowlevel_init:
117	mov r10, lr
118
119	core_init
120
121	init_aips
122
123	init_max
124
125	init_m3if
126
127	init_clock
128	init_debug_board
129
130	cmp pc, #PHYS_SDRAM_1
131	blo init_sdram_start
132	cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
133	blo skip_sdram_setup
134
135init_sdram_start:
136	/*init_sdram*/
137	setup_sdram
138
139skip_sdram_setup:
140	mov lr, r10
141	mov pc, lr
142
143
144/*
145 * r0: ESDCTL control base, r1: sdram slot base
146 * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
147 */
148setup_sdram_bank:
149	mov r3, #0xE
150	tst r2, #0x1
151	orreq r3, r3, #0x300 /*DDR2*/
152	str r3, [r0, #0x10]
153	bic r3, r3, #0x00A
154	str r3, [r0, #0x10]
155	beq 2f
156
157	mov r3, #0x20000
1581:      subs r3, r3, #1
159	bne 1b
160
1612:      tst r2, #0x1
162	ldreq r3, =ESDCTL_DDR2_CONFIG
163	ldrne r3, =ESDCTL_MDDR_CONFIG
164	cmp r1, #CSD1_BASE_ADDR
165	strlo r3, [r0, #0x4]
166	strhs r3, [r0, #0xC]
167
168	ldr r3, =ESDCTL_0x92220000
169	strlo r3, [r0, #0x0]
170	strhs r3, [r0, #0x8]
171	mov r3, #0xDA
172	ldr r4, =ESDCTL_PRECHARGE
173	strb r3, [r1, r4]
174
175	tst r2, #0x1
176	bne skip_set_mode
177
178	cmp r1, #CSD1_BASE_ADDR
179	ldr r3, =ESDCTL_0xB2220000
180	strlo r3, [r0, #0x0]
181	strhs r3, [r0, #0x8]
182	mov r3, #0xDA
183	ldr r4, =ESDCTL_DDR2_EMR2
184	strb r3, [r1, r4]
185	ldr r4, =ESDCTL_DDR2_EMR3
186	strb r3, [r1, r4]
187	ldr r4, =ESDCTL_DDR2_EN_DLL
188	strb r3, [r1, r4]
189	ldr r4, =ESDCTL_DDR2_RESET_DLL
190	strb r3, [r1, r4]
191
192	ldr r3, =ESDCTL_0x92220000
193	strlo r3, [r0, #0x0]
194	strhs r3, [r0, #0x8]
195	mov r3, #0xDA
196	ldr r4, =ESDCTL_PRECHARGE
197	strb r3, [r1, r4]
198
199skip_set_mode:
200	cmp r1, #CSD1_BASE_ADDR
201	ldr r3, =ESDCTL_0xA2220000
202	strlo r3, [r0, #0x0]
203	strhs r3, [r0, #0x8]
204	mov r3, #0xDA
205	strb r3, [r1]
206	strb r3, [r1]
207
208	ldr r3, =ESDCTL_0xB2220000
209	strlo r3, [r0, #0x0]
210	strhs r3, [r0, #0x8]
211	tst r2, #0x1
212	ldreq r4, =ESDCTL_DDR2_MR
213	ldrne r4, =ESDCTL_MDDR_MR
214	mov r3, #0xDA
215	strb r3, [r1, r4]
216	ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
217	streqb r3, [r1, r4]
218	ldreq r4, =ESDCTL_DDR2_EN_DLL
219	ldrne r4, =ESDCTL_MDDR_EMR
220	strb r3, [r1, r4]
221
222	cmp r1, #CSD1_BASE_ADDR
223	ldr r3, =ESDCTL_0x82228080
224	strlo r3, [r0, #0x0]
225	strhs r3, [r0, #0x8]
226
227	tst r2, #0x1
228	moveq r4, #0x20000
229	movne r4, #0x200
2301:      subs r4, r4, #1
231	bne 1b
232
233	str r3, [r1, #0x100]
234	ldr r4, [r1, #0x100]
235	cmp r3, r4
236	movne r3, #1
237	moveq r3, #0
238
239	mov pc, lr
240