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Searched refs:EXTR_W (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsISelLowering.h115 EXTR_W, enumerator
DMipsDSPInstrInfo.td42 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
1211 def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;
1433 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
DMipsSEISelLowering.cpp2200 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp158 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.h167 EXTR_W, enumerator
DMipsDSPInstrInfo.td43 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
1216 def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;
1448 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
DMipsScheduleGeneric.td528 def : InstRW<[GenericDSPLong], (instregex "^EXTR_W$")>;
DMipsSEISelLowering.cpp2285 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W); in lowerINTRINSIC_W_CHAIN()
DMipsISelLowering.cpp240 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc973 {DBGFIELD("EXTR_W") 1, false, false, 35, 1, 13, 1, 0, 0}, // #698
1993 {DBGFIELD("EXTR_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #698
DMipsGenMCCodeEmitter.inc1348 UINT64_C(2080374840), // EXTR_W
5589 case Mips::EXTR_W: {
9074 Feature_HasDSP | 0, // EXTR_W = 1335
DMipsGenInstrInfo.inc1350 EXTR_W = 1335,
3355 EXTR_W = 698,
5395 …deEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo225, -1 ,nullptr }, // Inst #1335 = EXTR_W
9772 { Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM },
DMipsGenAsmWriter.inc2563 268460684U, // EXTR_W
5194 4U, // EXTR_W
DMipsGenDisassemblerTables.inc6026 /* 16366 */ MCD::OPC_Decode, 183, 10, 197, 2, // Opcode: EXTR_W
DMipsGenDAGISel.inc22211 /* 41081*/ /*SwitchOpcode*/ 39, TARGET_VAL(MipsISD::EXTR_W),// ->41123
22223 /* 41101*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTR_W), 0|OPFL_Chain,
22226 …// Dst: (EXTR_W:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, (imm:{ *:[i32] })<<P:Predicate_immZExt5>…
DMipsGenAsmMatcher.inc6173 …{ 3981 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,…
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc665 1107320605U, // EXTR_W
2379 0U, // EXTR_W
DMipsGenDisassemblerTables.inc3494 /* 12721 */ MCD_OPC_Decode, 136, 5, 187, 1, // Opcode: EXTR_W