1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 #include "MipsISelLowering.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MipsCCState.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/FunctionLoweringInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/GlobalVariable.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include <cctype>
41
42 using namespace llvm;
43
44 #define DEBUG_TYPE "mips-lower"
45
46 STATISTIC(NumTailCalls, "Number of tail calls");
47
48 static cl::opt<bool>
49 LargeGOT("mxgot", cl::Hidden,
50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
51
52 static cl::opt<bool>
53 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
54 cl::desc("MIPS: Don't trap on integer division by zero."),
55 cl::init(false));
56
57 static const MCPhysReg Mips64DPRegs[8] = {
58 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
59 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
60 };
61
62 // If I is a shifted mask, set the size (Size) and the first bit of the
63 // mask (Pos), and return true.
64 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
isShiftedMask(uint64_t I,uint64_t & Pos,uint64_t & Size)65 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
66 if (!isShiftedMask_64(I))
67 return false;
68
69 Size = countPopulation(I);
70 Pos = countTrailingZeros(I);
71 return true;
72 }
73
getGlobalReg(SelectionDAG & DAG,EVT Ty) const74 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
75 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
76 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
77 }
78
getTargetNode(GlobalAddressSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const79 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
80 SelectionDAG &DAG,
81 unsigned Flag) const {
82 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
83 }
84
getTargetNode(ExternalSymbolSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const85 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
86 SelectionDAG &DAG,
87 unsigned Flag) const {
88 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
89 }
90
getTargetNode(BlockAddressSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const91 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
92 SelectionDAG &DAG,
93 unsigned Flag) const {
94 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
95 }
96
getTargetNode(JumpTableSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const97 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
98 SelectionDAG &DAG,
99 unsigned Flag) const {
100 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
101 }
102
getTargetNode(ConstantPoolSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const103 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
104 SelectionDAG &DAG,
105 unsigned Flag) const {
106 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
107 N->getOffset(), Flag);
108 }
109
getTargetNodeName(unsigned Opcode) const110 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
111 switch ((MipsISD::NodeType)Opcode) {
112 case MipsISD::FIRST_NUMBER: break;
113 case MipsISD::JmpLink: return "MipsISD::JmpLink";
114 case MipsISD::TailCall: return "MipsISD::TailCall";
115 case MipsISD::Hi: return "MipsISD::Hi";
116 case MipsISD::Lo: return "MipsISD::Lo";
117 case MipsISD::GPRel: return "MipsISD::GPRel";
118 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
119 case MipsISD::Ret: return "MipsISD::Ret";
120 case MipsISD::ERet: return "MipsISD::ERet";
121 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
122 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
123 case MipsISD::FPCmp: return "MipsISD::FPCmp";
124 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
125 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
126 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
127 case MipsISD::MFHI: return "MipsISD::MFHI";
128 case MipsISD::MFLO: return "MipsISD::MFLO";
129 case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
130 case MipsISD::Mult: return "MipsISD::Mult";
131 case MipsISD::Multu: return "MipsISD::Multu";
132 case MipsISD::MAdd: return "MipsISD::MAdd";
133 case MipsISD::MAddu: return "MipsISD::MAddu";
134 case MipsISD::MSub: return "MipsISD::MSub";
135 case MipsISD::MSubu: return "MipsISD::MSubu";
136 case MipsISD::DivRem: return "MipsISD::DivRem";
137 case MipsISD::DivRemU: return "MipsISD::DivRemU";
138 case MipsISD::DivRem16: return "MipsISD::DivRem16";
139 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
140 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
141 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
142 case MipsISD::Wrapper: return "MipsISD::Wrapper";
143 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
144 case MipsISD::Sync: return "MipsISD::Sync";
145 case MipsISD::Ext: return "MipsISD::Ext";
146 case MipsISD::Ins: return "MipsISD::Ins";
147 case MipsISD::LWL: return "MipsISD::LWL";
148 case MipsISD::LWR: return "MipsISD::LWR";
149 case MipsISD::SWL: return "MipsISD::SWL";
150 case MipsISD::SWR: return "MipsISD::SWR";
151 case MipsISD::LDL: return "MipsISD::LDL";
152 case MipsISD::LDR: return "MipsISD::LDR";
153 case MipsISD::SDL: return "MipsISD::SDL";
154 case MipsISD::SDR: return "MipsISD::SDR";
155 case MipsISD::EXTP: return "MipsISD::EXTP";
156 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
157 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
158 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
159 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
160 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
161 case MipsISD::SHILO: return "MipsISD::SHILO";
162 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
163 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
164 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
165 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
166 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
167 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
168 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
169 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
170 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
171 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
172 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
173 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
174 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
175 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
176 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
177 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
178 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
179 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
180 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
181 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
182 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
183 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
184 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
185 case MipsISD::MULT: return "MipsISD::MULT";
186 case MipsISD::MULTU: return "MipsISD::MULTU";
187 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
188 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
189 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
190 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
191 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
192 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
193 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
194 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
195 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
196 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
197 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
198 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
199 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
200 case MipsISD::VCEQ: return "MipsISD::VCEQ";
201 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
202 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
203 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
204 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
205 case MipsISD::VSMAX: return "MipsISD::VSMAX";
206 case MipsISD::VSMIN: return "MipsISD::VSMIN";
207 case MipsISD::VUMAX: return "MipsISD::VUMAX";
208 case MipsISD::VUMIN: return "MipsISD::VUMIN";
209 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
210 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
211 case MipsISD::VNOR: return "MipsISD::VNOR";
212 case MipsISD::VSHF: return "MipsISD::VSHF";
213 case MipsISD::SHF: return "MipsISD::SHF";
214 case MipsISD::ILVEV: return "MipsISD::ILVEV";
215 case MipsISD::ILVOD: return "MipsISD::ILVOD";
216 case MipsISD::ILVL: return "MipsISD::ILVL";
217 case MipsISD::ILVR: return "MipsISD::ILVR";
218 case MipsISD::PCKEV: return "MipsISD::PCKEV";
219 case MipsISD::PCKOD: return "MipsISD::PCKOD";
220 case MipsISD::INSVE: return "MipsISD::INSVE";
221 }
222 return nullptr;
223 }
224
MipsTargetLowering(const MipsTargetMachine & TM,const MipsSubtarget & STI)225 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
226 const MipsSubtarget &STI)
227 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
228 // Mips does not have i1 type, so use i32 for
229 // setcc operations results (slt, sgt, ...).
230 setBooleanContents(ZeroOrOneBooleanContent);
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
232 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
233 // does. Integer booleans still use 0 and 1.
234 if (Subtarget.hasMips32r6())
235 setBooleanContents(ZeroOrOneBooleanContent,
236 ZeroOrNegativeOneBooleanContent);
237
238 // Load extented operations for i1 types must be promoted
239 for (MVT VT : MVT::integer_valuetypes()) {
240 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
241 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
242 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
243 }
244
245 // MIPS doesn't have extending float->double load/store. Set LoadExtAction
246 // for f32, f16
247 for (MVT VT : MVT::fp_valuetypes()) {
248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
249 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
250 }
251
252 // Set LoadExtAction for f16 vectors to Expand
253 for (MVT VT : MVT::fp_vector_valuetypes()) {
254 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
255 if (F16VT.isValid())
256 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
257 }
258
259 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
260 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
261
262 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
263
264 // Used by legalize types to correctly generate the setcc result.
265 // Without this, every float setcc comes with a AND/OR with the result,
266 // we don't want this, since the fpcmp result goes to a flag register,
267 // which is used implicitly by brcond and select operations.
268 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
269
270 // Mips Custom Operations
271 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
272 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
273 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
274 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
275 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
276 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
277 setOperationAction(ISD::SELECT, MVT::f32, Custom);
278 setOperationAction(ISD::SELECT, MVT::f64, Custom);
279 setOperationAction(ISD::SELECT, MVT::i32, Custom);
280 setOperationAction(ISD::SETCC, MVT::f32, Custom);
281 setOperationAction(ISD::SETCC, MVT::f64, Custom);
282 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
284 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
285 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
286
287 if (Subtarget.isGP64bit()) {
288 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
289 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
290 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
291 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
292 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
293 setOperationAction(ISD::SELECT, MVT::i64, Custom);
294 setOperationAction(ISD::LOAD, MVT::i64, Custom);
295 setOperationAction(ISD::STORE, MVT::i64, Custom);
296 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
297 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
298 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
299 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
300 }
301
302 if (!Subtarget.isGP64bit()) {
303 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
304 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
305 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
306 }
307
308 setOperationAction(ISD::ADD, MVT::i32, Custom);
309 if (Subtarget.isGP64bit())
310 setOperationAction(ISD::ADD, MVT::i64, Custom);
311
312 setOperationAction(ISD::SDIV, MVT::i32, Expand);
313 setOperationAction(ISD::SREM, MVT::i32, Expand);
314 setOperationAction(ISD::UDIV, MVT::i32, Expand);
315 setOperationAction(ISD::UREM, MVT::i32, Expand);
316 setOperationAction(ISD::SDIV, MVT::i64, Expand);
317 setOperationAction(ISD::SREM, MVT::i64, Expand);
318 setOperationAction(ISD::UDIV, MVT::i64, Expand);
319 setOperationAction(ISD::UREM, MVT::i64, Expand);
320
321 // Operations not directly supported by Mips.
322 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
323 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
324 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
325 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
326 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
327 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
328 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
329 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
330 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
331 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
332 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
334 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
335 if (Subtarget.hasCnMips()) {
336 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
337 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
338 } else {
339 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
340 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
341 }
342 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
343 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
344 setOperationAction(ISD::ROTL, MVT::i32, Expand);
345 setOperationAction(ISD::ROTL, MVT::i64, Expand);
346 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
347 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
348
349 if (!Subtarget.hasMips32r2())
350 setOperationAction(ISD::ROTR, MVT::i32, Expand);
351
352 if (!Subtarget.hasMips64r2())
353 setOperationAction(ISD::ROTR, MVT::i64, Expand);
354
355 setOperationAction(ISD::FSIN, MVT::f32, Expand);
356 setOperationAction(ISD::FSIN, MVT::f64, Expand);
357 setOperationAction(ISD::FCOS, MVT::f32, Expand);
358 setOperationAction(ISD::FCOS, MVT::f64, Expand);
359 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
360 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
361 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
362 setOperationAction(ISD::FPOW, MVT::f32, Expand);
363 setOperationAction(ISD::FPOW, MVT::f64, Expand);
364 setOperationAction(ISD::FLOG, MVT::f32, Expand);
365 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
366 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
367 setOperationAction(ISD::FEXP, MVT::f32, Expand);
368 setOperationAction(ISD::FMA, MVT::f32, Expand);
369 setOperationAction(ISD::FMA, MVT::f64, Expand);
370 setOperationAction(ISD::FREM, MVT::f32, Expand);
371 setOperationAction(ISD::FREM, MVT::f64, Expand);
372
373 // Lower f16 conversion operations into library calls
374 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
375 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
377 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
378
379 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
380
381 setOperationAction(ISD::VASTART, MVT::Other, Custom);
382 setOperationAction(ISD::VAARG, MVT::Other, Custom);
383 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
384 setOperationAction(ISD::VAEND, MVT::Other, Expand);
385
386 // Use the default for now
387 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
388 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
389
390 if (!Subtarget.isGP64bit()) {
391 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
392 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
393 }
394
395
396 if (!Subtarget.hasMips32r2()) {
397 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
398 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
399 }
400
401 // MIPS16 lacks MIPS32's clz and clo instructions.
402 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
403 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
404 if (!Subtarget.hasMips64())
405 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
406
407 if (!Subtarget.hasMips32r2())
408 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
409 if (!Subtarget.hasMips64r2())
410 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
411
412 if (Subtarget.isGP64bit()) {
413 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
414 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
415 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
416 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
417 }
418
419 setOperationAction(ISD::TRAP, MVT::Other, Legal);
420
421 setTargetDAGCombine(ISD::SDIVREM);
422 setTargetDAGCombine(ISD::UDIVREM);
423 setTargetDAGCombine(ISD::SELECT);
424 setTargetDAGCombine(ISD::AND);
425 setTargetDAGCombine(ISD::OR);
426 setTargetDAGCombine(ISD::ADD);
427 setTargetDAGCombine(ISD::AssertZext);
428
429 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
430
431 // The arguments on the stack are defined in terms of 4-byte slots on O32
432 // and 8-byte slots on N32/N64.
433 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
434
435 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
436
437 MaxStoresPerMemcpy = 16;
438
439 isMicroMips = Subtarget.inMicroMipsMode();
440 }
441
create(const MipsTargetMachine & TM,const MipsSubtarget & STI)442 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
443 const MipsSubtarget &STI) {
444 if (STI.inMips16Mode())
445 return llvm::createMips16TargetLowering(TM, STI);
446
447 return llvm::createMipsSETargetLowering(TM, STI);
448 }
449
450 // Create a fast isel object.
451 FastISel *
createFastISel(FunctionLoweringInfo & funcInfo,const TargetLibraryInfo * libInfo) const452 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
453 const TargetLibraryInfo *libInfo) const {
454 if (!funcInfo.MF->getTarget().Options.EnableFastISel)
455 return TargetLowering::createFastISel(funcInfo, libInfo);
456 return Mips::createFastISel(funcInfo, libInfo);
457 }
458
getSetCCResultType(const DataLayout &,LLVMContext &,EVT VT) const459 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
460 EVT VT) const {
461 if (!VT.isVector())
462 return MVT::i32;
463 return VT.changeVectorElementTypeToInteger();
464 }
465
performDivRemCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)466 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
467 TargetLowering::DAGCombinerInfo &DCI,
468 const MipsSubtarget &Subtarget) {
469 if (DCI.isBeforeLegalizeOps())
470 return SDValue();
471
472 EVT Ty = N->getValueType(0);
473 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
474 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
475 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
476 MipsISD::DivRemU16;
477 SDLoc DL(N);
478
479 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
480 N->getOperand(0), N->getOperand(1));
481 SDValue InChain = DAG.getEntryNode();
482 SDValue InGlue = DivRem;
483
484 // insert MFLO
485 if (N->hasAnyUseOfValue(0)) {
486 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
487 InGlue);
488 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
489 InChain = CopyFromLo.getValue(1);
490 InGlue = CopyFromLo.getValue(2);
491 }
492
493 // insert MFHI
494 if (N->hasAnyUseOfValue(1)) {
495 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
496 HI, Ty, InGlue);
497 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
498 }
499
500 return SDValue();
501 }
502
condCodeToFCC(ISD::CondCode CC)503 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
504 switch (CC) {
505 default: llvm_unreachable("Unknown fp condition code!");
506 case ISD::SETEQ:
507 case ISD::SETOEQ: return Mips::FCOND_OEQ;
508 case ISD::SETUNE: return Mips::FCOND_UNE;
509 case ISD::SETLT:
510 case ISD::SETOLT: return Mips::FCOND_OLT;
511 case ISD::SETGT:
512 case ISD::SETOGT: return Mips::FCOND_OGT;
513 case ISD::SETLE:
514 case ISD::SETOLE: return Mips::FCOND_OLE;
515 case ISD::SETGE:
516 case ISD::SETOGE: return Mips::FCOND_OGE;
517 case ISD::SETULT: return Mips::FCOND_ULT;
518 case ISD::SETULE: return Mips::FCOND_ULE;
519 case ISD::SETUGT: return Mips::FCOND_UGT;
520 case ISD::SETUGE: return Mips::FCOND_UGE;
521 case ISD::SETUO: return Mips::FCOND_UN;
522 case ISD::SETO: return Mips::FCOND_OR;
523 case ISD::SETNE:
524 case ISD::SETONE: return Mips::FCOND_ONE;
525 case ISD::SETUEQ: return Mips::FCOND_UEQ;
526 }
527 }
528
529
530 /// This function returns true if the floating point conditional branches and
531 /// conditional moves which use condition code CC should be inverted.
invertFPCondCodeUser(Mips::CondCode CC)532 static bool invertFPCondCodeUser(Mips::CondCode CC) {
533 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
534 return false;
535
536 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
537 "Illegal Condition Code");
538
539 return true;
540 }
541
542 // Creates and returns an FPCmp node from a setcc node.
543 // Returns Op if setcc is not a floating point comparison.
createFPCmp(SelectionDAG & DAG,const SDValue & Op)544 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
545 // must be a SETCC node
546 if (Op.getOpcode() != ISD::SETCC)
547 return Op;
548
549 SDValue LHS = Op.getOperand(0);
550
551 if (!LHS.getValueType().isFloatingPoint())
552 return Op;
553
554 SDValue RHS = Op.getOperand(1);
555 SDLoc DL(Op);
556
557 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
558 // node if necessary.
559 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
560
561 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
562 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
563 }
564
565 // Creates and returns a CMovFPT/F node.
createCMovFP(SelectionDAG & DAG,SDValue Cond,SDValue True,SDValue False,const SDLoc & DL)566 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
567 SDValue False, const SDLoc &DL) {
568 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
569 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
570 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
571
572 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
573 True.getValueType(), True, FCC0, False, Cond);
574 }
575
performSELECTCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)576 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
577 TargetLowering::DAGCombinerInfo &DCI,
578 const MipsSubtarget &Subtarget) {
579 if (DCI.isBeforeLegalizeOps())
580 return SDValue();
581
582 SDValue SetCC = N->getOperand(0);
583
584 if ((SetCC.getOpcode() != ISD::SETCC) ||
585 !SetCC.getOperand(0).getValueType().isInteger())
586 return SDValue();
587
588 SDValue False = N->getOperand(2);
589 EVT FalseTy = False.getValueType();
590
591 if (!FalseTy.isInteger())
592 return SDValue();
593
594 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
595
596 // If the RHS (False) is 0, we swap the order of the operands
597 // of ISD::SELECT (obviously also inverting the condition) so that we can
598 // take advantage of conditional moves using the $0 register.
599 // Example:
600 // return (a != 0) ? x : 0;
601 // load $reg, x
602 // movz $reg, $0, a
603 if (!FalseC)
604 return SDValue();
605
606 const SDLoc DL(N);
607
608 if (!FalseC->getZExtValue()) {
609 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
610 SDValue True = N->getOperand(1);
611
612 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
613 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
614
615 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
616 }
617
618 // If both operands are integer constants there's a possibility that we
619 // can do some interesting optimizations.
620 SDValue True = N->getOperand(1);
621 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
622
623 if (!TrueC || !True.getValueType().isInteger())
624 return SDValue();
625
626 // We'll also ignore MVT::i64 operands as this optimizations proves
627 // to be ineffective because of the required sign extensions as the result
628 // of a SETCC operator is always MVT::i32 for non-vector types.
629 if (True.getValueType() == MVT::i64)
630 return SDValue();
631
632 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
633
634 // 1) (a < x) ? y : y-1
635 // slti $reg1, a, x
636 // addiu $reg2, $reg1, y-1
637 if (Diff == 1)
638 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
639
640 // 2) (a < x) ? y-1 : y
641 // slti $reg1, a, x
642 // xor $reg1, $reg1, 1
643 // addiu $reg2, $reg1, y-1
644 if (Diff == -1) {
645 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
646 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
647 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
648 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
649 }
650
651 // Couldn't optimize.
652 return SDValue();
653 }
654
performCMovFPCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)655 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
656 TargetLowering::DAGCombinerInfo &DCI,
657 const MipsSubtarget &Subtarget) {
658 if (DCI.isBeforeLegalizeOps())
659 return SDValue();
660
661 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
662
663 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
664 if (!FalseC || FalseC->getZExtValue())
665 return SDValue();
666
667 // Since RHS (False) is 0, we swap the order of the True/False operands
668 // (obviously also inverting the condition) so that we can
669 // take advantage of conditional moves using the $0 register.
670 // Example:
671 // return (a != 0) ? x : 0;
672 // load $reg, x
673 // movz $reg, $0, a
674 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
675 MipsISD::CMovFP_T;
676
677 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
678 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
679 ValueIfFalse, FCC, ValueIfTrue, Glue);
680 }
681
performANDCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)682 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
683 TargetLowering::DAGCombinerInfo &DCI,
684 const MipsSubtarget &Subtarget) {
685 // Pattern match EXT.
686 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
687 // => ext $dst, $src, size, pos
688 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
689 return SDValue();
690
691 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
692 unsigned ShiftRightOpc = ShiftRight.getOpcode();
693
694 // Op's first operand must be a shift right.
695 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
696 return SDValue();
697
698 // The second operand of the shift must be an immediate.
699 ConstantSDNode *CN;
700 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
701 return SDValue();
702
703 uint64_t Pos = CN->getZExtValue();
704 uint64_t SMPos, SMSize;
705
706 // Op's second operand must be a shifted mask.
707 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
708 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
709 return SDValue();
710
711 // Return if the shifted mask does not start at bit 0 or the sum of its size
712 // and Pos exceeds the word's size.
713 EVT ValTy = N->getValueType(0);
714 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
715 return SDValue();
716
717 SDLoc DL(N);
718 return DAG.getNode(MipsISD::Ext, DL, ValTy,
719 ShiftRight.getOperand(0),
720 DAG.getConstant(Pos, DL, MVT::i32),
721 DAG.getConstant(SMSize, DL, MVT::i32));
722 }
723
performORCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)724 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
725 TargetLowering::DAGCombinerInfo &DCI,
726 const MipsSubtarget &Subtarget) {
727 // Pattern match INS.
728 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
729 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
730 // => ins $dst, $src, size, pos, $src1
731 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
732 return SDValue();
733
734 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
735 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
736 ConstantSDNode *CN;
737
738 // See if Op's first operand matches (and $src1 , mask0).
739 if (And0.getOpcode() != ISD::AND)
740 return SDValue();
741
742 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
743 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
744 return SDValue();
745
746 // See if Op's second operand matches (and (shl $src, pos), mask1).
747 if (And1.getOpcode() != ISD::AND)
748 return SDValue();
749
750 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
751 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
752 return SDValue();
753
754 // The shift masks must have the same position and size.
755 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
756 return SDValue();
757
758 SDValue Shl = And1.getOperand(0);
759 if (Shl.getOpcode() != ISD::SHL)
760 return SDValue();
761
762 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
763 return SDValue();
764
765 unsigned Shamt = CN->getZExtValue();
766
767 // Return if the shift amount and the first bit position of mask are not the
768 // same.
769 EVT ValTy = N->getValueType(0);
770 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
771 return SDValue();
772
773 SDLoc DL(N);
774 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
775 DAG.getConstant(SMPos0, DL, MVT::i32),
776 DAG.getConstant(SMSize0, DL, MVT::i32),
777 And0.getOperand(0));
778 }
779
performADDCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)780 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
781 TargetLowering::DAGCombinerInfo &DCI,
782 const MipsSubtarget &Subtarget) {
783 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
784
785 if (DCI.isBeforeLegalizeOps())
786 return SDValue();
787
788 SDValue Add = N->getOperand(1);
789
790 if (Add.getOpcode() != ISD::ADD)
791 return SDValue();
792
793 SDValue Lo = Add.getOperand(1);
794
795 if ((Lo.getOpcode() != MipsISD::Lo) ||
796 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
797 return SDValue();
798
799 EVT ValTy = N->getValueType(0);
800 SDLoc DL(N);
801
802 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
803 Add.getOperand(0));
804 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
805 }
806
performAssertZextCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)807 static SDValue performAssertZextCombine(SDNode *N, SelectionDAG &DAG,
808 TargetLowering::DAGCombinerInfo &DCI,
809 const MipsSubtarget &Subtarget) {
810 SDValue N0 = N->getOperand(0);
811 EVT NarrowerVT = cast<VTSDNode>(N->getOperand(1))->getVT();
812
813 if (N0.getOpcode() != ISD::TRUNCATE)
814 return SDValue();
815
816 if (N0.getOperand(0).getOpcode() != ISD::AssertZext)
817 return SDValue();
818
819 // fold (AssertZext (trunc (AssertZext x))) -> (trunc (AssertZext x))
820 // if the type of the extension of the innermost AssertZext node is
821 // smaller from that of the outermost node, eg:
822 // (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8)
823 // -> (trunc:i32 (AssertZext X, i8))
824 SDValue WiderAssertZext = N0.getOperand(0);
825 EVT WiderVT = cast<VTSDNode>(WiderAssertZext->getOperand(1))->getVT();
826
827 if (NarrowerVT.bitsLT(WiderVT)) {
828 SDValue NewAssertZext = DAG.getNode(
829 ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(),
830 WiderAssertZext.getOperand(0), DAG.getValueType(NarrowerVT));
831 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0),
832 NewAssertZext);
833 }
834
835 return SDValue();
836 }
837
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const838 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
839 const {
840 SelectionDAG &DAG = DCI.DAG;
841 unsigned Opc = N->getOpcode();
842
843 switch (Opc) {
844 default: break;
845 case ISD::SDIVREM:
846 case ISD::UDIVREM:
847 return performDivRemCombine(N, DAG, DCI, Subtarget);
848 case ISD::SELECT:
849 return performSELECTCombine(N, DAG, DCI, Subtarget);
850 case MipsISD::CMovFP_F:
851 case MipsISD::CMovFP_T:
852 return performCMovFPCombine(N, DAG, DCI, Subtarget);
853 case ISD::AND:
854 return performANDCombine(N, DAG, DCI, Subtarget);
855 case ISD::OR:
856 return performORCombine(N, DAG, DCI, Subtarget);
857 case ISD::ADD:
858 return performADDCombine(N, DAG, DCI, Subtarget);
859 case ISD::AssertZext:
860 return performAssertZextCombine(N, DAG, DCI, Subtarget);
861 }
862
863 return SDValue();
864 }
865
isCheapToSpeculateCttz() const866 bool MipsTargetLowering::isCheapToSpeculateCttz() const {
867 return Subtarget.hasMips32();
868 }
869
isCheapToSpeculateCtlz() const870 bool MipsTargetLowering::isCheapToSpeculateCtlz() const {
871 return Subtarget.hasMips32();
872 }
873
874 void
LowerOperationWrapper(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const875 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
876 SmallVectorImpl<SDValue> &Results,
877 SelectionDAG &DAG) const {
878 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
879
880 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
881 Results.push_back(Res.getValue(I));
882 }
883
884 void
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const885 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
886 SmallVectorImpl<SDValue> &Results,
887 SelectionDAG &DAG) const {
888 return LowerOperationWrapper(N, Results, DAG);
889 }
890
891 SDValue MipsTargetLowering::
LowerOperation(SDValue Op,SelectionDAG & DAG) const892 LowerOperation(SDValue Op, SelectionDAG &DAG) const
893 {
894 switch (Op.getOpcode())
895 {
896 case ISD::BR_JT: return lowerBR_JT(Op, DAG);
897 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
898 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
899 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
900 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
901 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
902 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
903 case ISD::SELECT: return lowerSELECT(Op, DAG);
904 case ISD::SETCC: return lowerSETCC(Op, DAG);
905 case ISD::VASTART: return lowerVASTART(Op, DAG);
906 case ISD::VAARG: return lowerVAARG(Op, DAG);
907 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
908 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
909 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
910 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
911 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
912 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
913 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
914 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
915 case ISD::LOAD: return lowerLOAD(Op, DAG);
916 case ISD::STORE: return lowerSTORE(Op, DAG);
917 case ISD::ADD: return lowerADD(Op, DAG);
918 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
919 }
920 return SDValue();
921 }
922
923 //===----------------------------------------------------------------------===//
924 // Lower helper functions
925 //===----------------------------------------------------------------------===//
926
927 // addLiveIn - This helper function adds the specified physical register to the
928 // MachineFunction as a live in value. It also creates a corresponding
929 // virtual register for it.
930 static unsigned
addLiveIn(MachineFunction & MF,unsigned PReg,const TargetRegisterClass * RC)931 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
932 {
933 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
934 MF.getRegInfo().addLiveIn(PReg, VReg);
935 return VReg;
936 }
937
insertDivByZeroTrap(MachineInstr & MI,MachineBasicBlock & MBB,const TargetInstrInfo & TII,bool Is64Bit,bool IsMicroMips)938 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
939 MachineBasicBlock &MBB,
940 const TargetInstrInfo &TII,
941 bool Is64Bit, bool IsMicroMips) {
942 if (NoZeroDivCheck)
943 return &MBB;
944
945 // Insert instruction "teq $divisor_reg, $zero, 7".
946 MachineBasicBlock::iterator I(MI);
947 MachineInstrBuilder MIB;
948 MachineOperand &Divisor = MI.getOperand(2);
949 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
950 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
951 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
952 .addReg(Mips::ZERO)
953 .addImm(7);
954
955 // Use the 32-bit sub-register if this is a 64-bit division.
956 if (Is64Bit)
957 MIB->getOperand(0).setSubReg(Mips::sub_32);
958
959 // Clear Divisor's kill flag.
960 Divisor.setIsKill(false);
961
962 // We would normally delete the original instruction here but in this case
963 // we only needed to inject an additional instruction rather than replace it.
964
965 return &MBB;
966 }
967
968 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr & MI,MachineBasicBlock * BB) const969 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
970 MachineBasicBlock *BB) const {
971 switch (MI.getOpcode()) {
972 default:
973 llvm_unreachable("Unexpected instr type to insert");
974 case Mips::ATOMIC_LOAD_ADD_I8:
975 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
976 case Mips::ATOMIC_LOAD_ADD_I16:
977 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
978 case Mips::ATOMIC_LOAD_ADD_I32:
979 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
980 case Mips::ATOMIC_LOAD_ADD_I64:
981 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
982
983 case Mips::ATOMIC_LOAD_AND_I8:
984 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
985 case Mips::ATOMIC_LOAD_AND_I16:
986 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
987 case Mips::ATOMIC_LOAD_AND_I32:
988 return emitAtomicBinary(MI, BB, 4, Mips::AND);
989 case Mips::ATOMIC_LOAD_AND_I64:
990 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
991
992 case Mips::ATOMIC_LOAD_OR_I8:
993 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
994 case Mips::ATOMIC_LOAD_OR_I16:
995 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
996 case Mips::ATOMIC_LOAD_OR_I32:
997 return emitAtomicBinary(MI, BB, 4, Mips::OR);
998 case Mips::ATOMIC_LOAD_OR_I64:
999 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
1000
1001 case Mips::ATOMIC_LOAD_XOR_I8:
1002 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1003 case Mips::ATOMIC_LOAD_XOR_I16:
1004 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1005 case Mips::ATOMIC_LOAD_XOR_I32:
1006 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
1007 case Mips::ATOMIC_LOAD_XOR_I64:
1008 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
1009
1010 case Mips::ATOMIC_LOAD_NAND_I8:
1011 return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
1012 case Mips::ATOMIC_LOAD_NAND_I16:
1013 return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
1014 case Mips::ATOMIC_LOAD_NAND_I32:
1015 return emitAtomicBinary(MI, BB, 4, 0, true);
1016 case Mips::ATOMIC_LOAD_NAND_I64:
1017 return emitAtomicBinary(MI, BB, 8, 0, true);
1018
1019 case Mips::ATOMIC_LOAD_SUB_I8:
1020 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1021 case Mips::ATOMIC_LOAD_SUB_I16:
1022 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1023 case Mips::ATOMIC_LOAD_SUB_I32:
1024 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
1025 case Mips::ATOMIC_LOAD_SUB_I64:
1026 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1027
1028 case Mips::ATOMIC_SWAP_I8:
1029 return emitAtomicBinaryPartword(MI, BB, 1, 0);
1030 case Mips::ATOMIC_SWAP_I16:
1031 return emitAtomicBinaryPartword(MI, BB, 2, 0);
1032 case Mips::ATOMIC_SWAP_I32:
1033 return emitAtomicBinary(MI, BB, 4, 0);
1034 case Mips::ATOMIC_SWAP_I64:
1035 return emitAtomicBinary(MI, BB, 8, 0);
1036
1037 case Mips::ATOMIC_CMP_SWAP_I8:
1038 return emitAtomicCmpSwapPartword(MI, BB, 1);
1039 case Mips::ATOMIC_CMP_SWAP_I16:
1040 return emitAtomicCmpSwapPartword(MI, BB, 2);
1041 case Mips::ATOMIC_CMP_SWAP_I32:
1042 return emitAtomicCmpSwap(MI, BB, 4);
1043 case Mips::ATOMIC_CMP_SWAP_I64:
1044 return emitAtomicCmpSwap(MI, BB, 8);
1045 case Mips::PseudoSDIV:
1046 case Mips::PseudoUDIV:
1047 case Mips::DIV:
1048 case Mips::DIVU:
1049 case Mips::MOD:
1050 case Mips::MODU:
1051 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1052 false);
1053 case Mips::SDIV_MM_Pseudo:
1054 case Mips::UDIV_MM_Pseudo:
1055 case Mips::SDIV_MM:
1056 case Mips::UDIV_MM:
1057 case Mips::DIV_MMR6:
1058 case Mips::DIVU_MMR6:
1059 case Mips::MOD_MMR6:
1060 case Mips::MODU_MMR6:
1061 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1062 case Mips::PseudoDSDIV:
1063 case Mips::PseudoDUDIV:
1064 case Mips::DDIV:
1065 case Mips::DDIVU:
1066 case Mips::DMOD:
1067 case Mips::DMODU:
1068 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1069 case Mips::DDIV_MM64R6:
1070 case Mips::DDIVU_MM64R6:
1071 case Mips::DMOD_MM64R6:
1072 case Mips::DMODU_MM64R6:
1073 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true);
1074 case Mips::SEL_D:
1075 case Mips::SEL_D_MMR6:
1076 return emitSEL_D(MI, BB);
1077
1078 case Mips::PseudoSELECT_I:
1079 case Mips::PseudoSELECT_I64:
1080 case Mips::PseudoSELECT_S:
1081 case Mips::PseudoSELECT_D32:
1082 case Mips::PseudoSELECT_D64:
1083 return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1084 case Mips::PseudoSELECTFP_F_I:
1085 case Mips::PseudoSELECTFP_F_I64:
1086 case Mips::PseudoSELECTFP_F_S:
1087 case Mips::PseudoSELECTFP_F_D32:
1088 case Mips::PseudoSELECTFP_F_D64:
1089 return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1090 case Mips::PseudoSELECTFP_T_I:
1091 case Mips::PseudoSELECTFP_T_I64:
1092 case Mips::PseudoSELECTFP_T_S:
1093 case Mips::PseudoSELECTFP_T_D32:
1094 case Mips::PseudoSELECTFP_T_D64:
1095 return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1096 }
1097 }
1098
1099 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1100 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
emitAtomicBinary(MachineInstr & MI,MachineBasicBlock * BB,unsigned Size,unsigned BinOpcode,bool Nand) const1101 MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1102 MachineBasicBlock *BB,
1103 unsigned Size,
1104 unsigned BinOpcode,
1105 bool Nand) const {
1106 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1107
1108 MachineFunction *MF = BB->getParent();
1109 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1110 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1111 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1112 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1113 DebugLoc DL = MI.getDebugLoc();
1114 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1115
1116 if (Size == 4) {
1117 if (isMicroMips) {
1118 LL = Mips::LL_MM;
1119 SC = Mips::SC_MM;
1120 } else {
1121 LL = Subtarget.hasMips32r6()
1122 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1123 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1124 SC = Subtarget.hasMips32r6()
1125 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1126 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1127 }
1128
1129 AND = Mips::AND;
1130 NOR = Mips::NOR;
1131 ZERO = Mips::ZERO;
1132 BEQ = Mips::BEQ;
1133 } else {
1134 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1135 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1136 AND = Mips::AND64;
1137 NOR = Mips::NOR64;
1138 ZERO = Mips::ZERO_64;
1139 BEQ = Mips::BEQ64;
1140 }
1141
1142 unsigned OldVal = MI.getOperand(0).getReg();
1143 unsigned Ptr = MI.getOperand(1).getReg();
1144 unsigned Incr = MI.getOperand(2).getReg();
1145
1146 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1147 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1148 unsigned Success = RegInfo.createVirtualRegister(RC);
1149
1150 // insert new blocks after the current block
1151 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1152 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1153 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1154 MachineFunction::iterator It = ++BB->getIterator();
1155 MF->insert(It, loopMBB);
1156 MF->insert(It, exitMBB);
1157
1158 // Transfer the remainder of BB and its successor edges to exitMBB.
1159 exitMBB->splice(exitMBB->begin(), BB,
1160 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1161 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1162
1163 // thisMBB:
1164 // ...
1165 // fallthrough --> loopMBB
1166 BB->addSuccessor(loopMBB);
1167 loopMBB->addSuccessor(loopMBB);
1168 loopMBB->addSuccessor(exitMBB);
1169
1170 // loopMBB:
1171 // ll oldval, 0(ptr)
1172 // <binop> storeval, oldval, incr
1173 // sc success, storeval, 0(ptr)
1174 // beq success, $0, loopMBB
1175 BB = loopMBB;
1176 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1177 if (Nand) {
1178 // and andres, oldval, incr
1179 // nor storeval, $0, andres
1180 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1181 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1182 } else if (BinOpcode) {
1183 // <binop> storeval, oldval, incr
1184 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1185 } else {
1186 StoreVal = Incr;
1187 }
1188 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1189 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1190
1191 MI.eraseFromParent(); // The instruction is gone now.
1192
1193 return exitMBB;
1194 }
1195
emitSignExtendToI32InReg(MachineInstr & MI,MachineBasicBlock * BB,unsigned Size,unsigned DstReg,unsigned SrcReg) const1196 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1197 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1198 unsigned SrcReg) const {
1199 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1200 const DebugLoc &DL = MI.getDebugLoc();
1201
1202 if (Subtarget.hasMips32r2() && Size == 1) {
1203 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1204 return BB;
1205 }
1206
1207 if (Subtarget.hasMips32r2() && Size == 2) {
1208 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1209 return BB;
1210 }
1211
1212 MachineFunction *MF = BB->getParent();
1213 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1214 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1215 unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1216
1217 assert(Size < 32);
1218 int64_t ShiftImm = 32 - (Size * 8);
1219
1220 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1221 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1222
1223 return BB;
1224 }
1225
emitAtomicBinaryPartword(MachineInstr & MI,MachineBasicBlock * BB,unsigned Size,unsigned BinOpcode,bool Nand) const1226 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1227 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
1228 bool Nand) const {
1229 assert((Size == 1 || Size == 2) &&
1230 "Unsupported size for EmitAtomicBinaryPartial.");
1231
1232 MachineFunction *MF = BB->getParent();
1233 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1234 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1235 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1236 const TargetRegisterClass *RCp =
1237 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1238 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1239 DebugLoc DL = MI.getDebugLoc();
1240
1241 unsigned Dest = MI.getOperand(0).getReg();
1242 unsigned Ptr = MI.getOperand(1).getReg();
1243 unsigned Incr = MI.getOperand(2).getReg();
1244
1245 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1246 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1247 unsigned Mask = RegInfo.createVirtualRegister(RC);
1248 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1249 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1250 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1251 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1252 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1253 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1254 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1255 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1256 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1257 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1258 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1259 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1260 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1261 unsigned Success = RegInfo.createVirtualRegister(RC);
1262
1263 unsigned LL, SC;
1264 if (isMicroMips) {
1265 LL = Mips::LL_MM;
1266 SC = Mips::SC_MM;
1267 } else {
1268 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1269 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1270 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1271 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1272 }
1273
1274 // insert new blocks after the current block
1275 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1276 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1277 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1278 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1279 MachineFunction::iterator It = ++BB->getIterator();
1280 MF->insert(It, loopMBB);
1281 MF->insert(It, sinkMBB);
1282 MF->insert(It, exitMBB);
1283
1284 // Transfer the remainder of BB and its successor edges to exitMBB.
1285 exitMBB->splice(exitMBB->begin(), BB,
1286 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1287 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1288
1289 BB->addSuccessor(loopMBB);
1290 loopMBB->addSuccessor(loopMBB);
1291 loopMBB->addSuccessor(sinkMBB);
1292 sinkMBB->addSuccessor(exitMBB);
1293
1294 // thisMBB:
1295 // addiu masklsb2,$0,-4 # 0xfffffffc
1296 // and alignedaddr,ptr,masklsb2
1297 // andi ptrlsb2,ptr,3
1298 // sll shiftamt,ptrlsb2,3
1299 // ori maskupper,$0,255 # 0xff
1300 // sll mask,maskupper,shiftamt
1301 // nor mask2,$0,mask
1302 // sll incr2,incr,shiftamt
1303
1304 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1305 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1306 .addReg(ABI.GetNullPtr()).addImm(-4);
1307 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1308 .addReg(Ptr).addReg(MaskLSB2);
1309 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1310 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1311 if (Subtarget.isLittle()) {
1312 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1313 } else {
1314 unsigned Off = RegInfo.createVirtualRegister(RC);
1315 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1316 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1317 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1318 }
1319 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1320 .addReg(Mips::ZERO).addImm(MaskImm);
1321 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1322 .addReg(MaskUpper).addReg(ShiftAmt);
1323 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1324 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1325
1326 // atomic.load.binop
1327 // loopMBB:
1328 // ll oldval,0(alignedaddr)
1329 // binop binopres,oldval,incr2
1330 // and newval,binopres,mask
1331 // and maskedoldval0,oldval,mask2
1332 // or storeval,maskedoldval0,newval
1333 // sc success,storeval,0(alignedaddr)
1334 // beq success,$0,loopMBB
1335
1336 // atomic.swap
1337 // loopMBB:
1338 // ll oldval,0(alignedaddr)
1339 // and newval,incr2,mask
1340 // and maskedoldval0,oldval,mask2
1341 // or storeval,maskedoldval0,newval
1342 // sc success,storeval,0(alignedaddr)
1343 // beq success,$0,loopMBB
1344
1345 BB = loopMBB;
1346 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1347 if (Nand) {
1348 // and andres, oldval, incr2
1349 // nor binopres, $0, andres
1350 // and newval, binopres, mask
1351 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1352 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1353 .addReg(Mips::ZERO).addReg(AndRes);
1354 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1355 } else if (BinOpcode) {
1356 // <binop> binopres, oldval, incr2
1357 // and newval, binopres, mask
1358 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1359 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1360 } else { // atomic.swap
1361 // and newval, incr2, mask
1362 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1363 }
1364
1365 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1366 .addReg(OldVal).addReg(Mask2);
1367 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1368 .addReg(MaskedOldVal0).addReg(NewVal);
1369 BuildMI(BB, DL, TII->get(SC), Success)
1370 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1371 BuildMI(BB, DL, TII->get(Mips::BEQ))
1372 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1373
1374 // sinkMBB:
1375 // and maskedoldval1,oldval,mask
1376 // srl srlres,maskedoldval1,shiftamt
1377 // sign_extend dest,srlres
1378 BB = sinkMBB;
1379
1380 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1381 .addReg(OldVal).addReg(Mask);
1382 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1383 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1384 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1385
1386 MI.eraseFromParent(); // The instruction is gone now.
1387
1388 return exitMBB;
1389 }
1390
emitAtomicCmpSwap(MachineInstr & MI,MachineBasicBlock * BB,unsigned Size) const1391 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1392 MachineBasicBlock *BB,
1393 unsigned Size) const {
1394 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1395
1396 MachineFunction *MF = BB->getParent();
1397 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1398 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1399 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1400 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1401 DebugLoc DL = MI.getDebugLoc();
1402 unsigned LL, SC, ZERO, BNE, BEQ;
1403
1404 if (Size == 4) {
1405 if (isMicroMips) {
1406 LL = Mips::LL_MM;
1407 SC = Mips::SC_MM;
1408 } else {
1409 LL = Subtarget.hasMips32r6()
1410 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1411 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1412 SC = Subtarget.hasMips32r6()
1413 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1414 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1415 }
1416
1417 ZERO = Mips::ZERO;
1418 BNE = Mips::BNE;
1419 BEQ = Mips::BEQ;
1420 } else {
1421 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1422 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1423 ZERO = Mips::ZERO_64;
1424 BNE = Mips::BNE64;
1425 BEQ = Mips::BEQ64;
1426 }
1427
1428 unsigned Dest = MI.getOperand(0).getReg();
1429 unsigned Ptr = MI.getOperand(1).getReg();
1430 unsigned OldVal = MI.getOperand(2).getReg();
1431 unsigned NewVal = MI.getOperand(3).getReg();
1432
1433 unsigned Success = RegInfo.createVirtualRegister(RC);
1434
1435 // insert new blocks after the current block
1436 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1437 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1438 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1439 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1440 MachineFunction::iterator It = ++BB->getIterator();
1441 MF->insert(It, loop1MBB);
1442 MF->insert(It, loop2MBB);
1443 MF->insert(It, exitMBB);
1444
1445 // Transfer the remainder of BB and its successor edges to exitMBB.
1446 exitMBB->splice(exitMBB->begin(), BB,
1447 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1448 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1449
1450 // thisMBB:
1451 // ...
1452 // fallthrough --> loop1MBB
1453 BB->addSuccessor(loop1MBB);
1454 loop1MBB->addSuccessor(exitMBB);
1455 loop1MBB->addSuccessor(loop2MBB);
1456 loop2MBB->addSuccessor(loop1MBB);
1457 loop2MBB->addSuccessor(exitMBB);
1458
1459 // loop1MBB:
1460 // ll dest, 0(ptr)
1461 // bne dest, oldval, exitMBB
1462 BB = loop1MBB;
1463 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1464 BuildMI(BB, DL, TII->get(BNE))
1465 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1466
1467 // loop2MBB:
1468 // sc success, newval, 0(ptr)
1469 // beq success, $0, loop1MBB
1470 BB = loop2MBB;
1471 BuildMI(BB, DL, TII->get(SC), Success)
1472 .addReg(NewVal).addReg(Ptr).addImm(0);
1473 BuildMI(BB, DL, TII->get(BEQ))
1474 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1475
1476 MI.eraseFromParent(); // The instruction is gone now.
1477
1478 return exitMBB;
1479 }
1480
emitAtomicCmpSwapPartword(MachineInstr & MI,MachineBasicBlock * BB,unsigned Size) const1481 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1482 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1483 assert((Size == 1 || Size == 2) &&
1484 "Unsupported size for EmitAtomicCmpSwapPartial.");
1485
1486 MachineFunction *MF = BB->getParent();
1487 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1488 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1489 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1490 const TargetRegisterClass *RCp =
1491 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1492 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1493 DebugLoc DL = MI.getDebugLoc();
1494
1495 unsigned Dest = MI.getOperand(0).getReg();
1496 unsigned Ptr = MI.getOperand(1).getReg();
1497 unsigned CmpVal = MI.getOperand(2).getReg();
1498 unsigned NewVal = MI.getOperand(3).getReg();
1499
1500 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1501 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1502 unsigned Mask = RegInfo.createVirtualRegister(RC);
1503 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1504 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1505 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1506 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1507 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1508 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1509 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1510 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1511 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1512 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1513 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1514 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1515 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1516 unsigned Success = RegInfo.createVirtualRegister(RC);
1517 unsigned LL, SC;
1518
1519 if (isMicroMips) {
1520 LL = Mips::LL_MM;
1521 SC = Mips::SC_MM;
1522 } else {
1523 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1524 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1525 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1526 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1527 }
1528
1529 // insert new blocks after the current block
1530 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1531 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1532 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1533 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1534 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1535 MachineFunction::iterator It = ++BB->getIterator();
1536 MF->insert(It, loop1MBB);
1537 MF->insert(It, loop2MBB);
1538 MF->insert(It, sinkMBB);
1539 MF->insert(It, exitMBB);
1540
1541 // Transfer the remainder of BB and its successor edges to exitMBB.
1542 exitMBB->splice(exitMBB->begin(), BB,
1543 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1544 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1545
1546 BB->addSuccessor(loop1MBB);
1547 loop1MBB->addSuccessor(sinkMBB);
1548 loop1MBB->addSuccessor(loop2MBB);
1549 loop2MBB->addSuccessor(loop1MBB);
1550 loop2MBB->addSuccessor(sinkMBB);
1551 sinkMBB->addSuccessor(exitMBB);
1552
1553 // FIXME: computation of newval2 can be moved to loop2MBB.
1554 // thisMBB:
1555 // addiu masklsb2,$0,-4 # 0xfffffffc
1556 // and alignedaddr,ptr,masklsb2
1557 // andi ptrlsb2,ptr,3
1558 // xori ptrlsb2,ptrlsb2,3 # Only for BE
1559 // sll shiftamt,ptrlsb2,3
1560 // ori maskupper,$0,255 # 0xff
1561 // sll mask,maskupper,shiftamt
1562 // nor mask2,$0,mask
1563 // andi maskedcmpval,cmpval,255
1564 // sll shiftedcmpval,maskedcmpval,shiftamt
1565 // andi maskednewval,newval,255
1566 // sll shiftednewval,maskednewval,shiftamt
1567 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1568 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1569 .addReg(ABI.GetNullPtr()).addImm(-4);
1570 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1571 .addReg(Ptr).addReg(MaskLSB2);
1572 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1573 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1574 if (Subtarget.isLittle()) {
1575 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1576 } else {
1577 unsigned Off = RegInfo.createVirtualRegister(RC);
1578 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1579 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1580 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1581 }
1582 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1583 .addReg(Mips::ZERO).addImm(MaskImm);
1584 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1585 .addReg(MaskUpper).addReg(ShiftAmt);
1586 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1587 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1588 .addReg(CmpVal).addImm(MaskImm);
1589 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1590 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1591 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1592 .addReg(NewVal).addImm(MaskImm);
1593 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1594 .addReg(MaskedNewVal).addReg(ShiftAmt);
1595
1596 // loop1MBB:
1597 // ll oldval,0(alginedaddr)
1598 // and maskedoldval0,oldval,mask
1599 // bne maskedoldval0,shiftedcmpval,sinkMBB
1600 BB = loop1MBB;
1601 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1602 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1603 .addReg(OldVal).addReg(Mask);
1604 BuildMI(BB, DL, TII->get(Mips::BNE))
1605 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1606
1607 // loop2MBB:
1608 // and maskedoldval1,oldval,mask2
1609 // or storeval,maskedoldval1,shiftednewval
1610 // sc success,storeval,0(alignedaddr)
1611 // beq success,$0,loop1MBB
1612 BB = loop2MBB;
1613 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1614 .addReg(OldVal).addReg(Mask2);
1615 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1616 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1617 BuildMI(BB, DL, TII->get(SC), Success)
1618 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1619 BuildMI(BB, DL, TII->get(Mips::BEQ))
1620 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1621
1622 // sinkMBB:
1623 // srl srlres,maskedoldval0,shiftamt
1624 // sign_extend dest,srlres
1625 BB = sinkMBB;
1626
1627 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1628 .addReg(MaskedOldVal0).addReg(ShiftAmt);
1629 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1630
1631 MI.eraseFromParent(); // The instruction is gone now.
1632
1633 return exitMBB;
1634 }
1635
emitSEL_D(MachineInstr & MI,MachineBasicBlock * BB) const1636 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr &MI,
1637 MachineBasicBlock *BB) const {
1638 MachineFunction *MF = BB->getParent();
1639 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1640 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1641 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1642 DebugLoc DL = MI.getDebugLoc();
1643 MachineBasicBlock::iterator II(MI);
1644
1645 unsigned Fc = MI.getOperand(1).getReg();
1646 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
1647
1648 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
1649
1650 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
1651 .addImm(0)
1652 .addReg(Fc)
1653 .addImm(Mips::sub_lo);
1654
1655 // We don't erase the original instruction, we just replace the condition
1656 // register with the 64-bit super-register.
1657 MI.getOperand(1).setReg(Fc2);
1658
1659 return BB;
1660 }
1661
1662 //===----------------------------------------------------------------------===//
1663 // Misc Lower Operation implementation
1664 //===----------------------------------------------------------------------===//
lowerBR_JT(SDValue Op,SelectionDAG & DAG) const1665 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1666 SDValue Chain = Op.getOperand(0);
1667 SDValue Table = Op.getOperand(1);
1668 SDValue Index = Op.getOperand(2);
1669 SDLoc DL(Op);
1670 auto &TD = DAG.getDataLayout();
1671 EVT PTy = getPointerTy(TD);
1672 unsigned EntrySize =
1673 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
1674
1675 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1676 DAG.getConstant(EntrySize, DL, PTy));
1677 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1678
1679 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
1680 Addr =
1681 DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1682 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()),
1683 MemVT, false, false, false, 0);
1684 Chain = Addr.getValue(1);
1685
1686 if (isPositionIndependent() || ABI.IsN64()) {
1687 // For PIC, the sequence is:
1688 // BRIND(load(Jumptable + index) + RelocBase)
1689 // RelocBase can be JumpTable, GOT or some sort of global base.
1690 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1691 getPICJumpTableRelocBase(Table, DAG));
1692 }
1693
1694 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1695 }
1696
lowerBRCOND(SDValue Op,SelectionDAG & DAG) const1697 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1698 // The first operand is the chain, the second is the condition, the third is
1699 // the block to branch to if the condition is true.
1700 SDValue Chain = Op.getOperand(0);
1701 SDValue Dest = Op.getOperand(2);
1702 SDLoc DL(Op);
1703
1704 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1705 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1706
1707 // Return if flag is not set by a floating point comparison.
1708 if (CondRes.getOpcode() != MipsISD::FPCmp)
1709 return Op;
1710
1711 SDValue CCNode = CondRes.getOperand(2);
1712 Mips::CondCode CC =
1713 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1714 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1715 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1716 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1717 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1718 FCC0, Dest, CondRes);
1719 }
1720
1721 SDValue MipsTargetLowering::
lowerSELECT(SDValue Op,SelectionDAG & DAG) const1722 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1723 {
1724 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1725 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1726
1727 // Return if flag is not set by a floating point comparison.
1728 if (Cond.getOpcode() != MipsISD::FPCmp)
1729 return Op;
1730
1731 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1732 SDLoc(Op));
1733 }
1734
lowerSETCC(SDValue Op,SelectionDAG & DAG) const1735 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1736 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1737 SDValue Cond = createFPCmp(DAG, Op);
1738
1739 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1740 "Floating point operand expected.");
1741
1742 SDLoc DL(Op);
1743 SDValue True = DAG.getConstant(1, DL, MVT::i32);
1744 SDValue False = DAG.getConstant(0, DL, MVT::i32);
1745
1746 return createCMovFP(DAG, Cond, True, False, DL);
1747 }
1748
lowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const1749 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1750 SelectionDAG &DAG) const {
1751 EVT Ty = Op.getValueType();
1752 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1753 const GlobalValue *GV = N->getGlobal();
1754
1755 if (!isPositionIndependent() && !ABI.IsN64()) {
1756 const MipsTargetObjectFile *TLOF =
1757 static_cast<const MipsTargetObjectFile *>(
1758 getTargetMachine().getObjFileLowering());
1759 if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine()))
1760 // %gp_rel relocation
1761 return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1762
1763 // %hi/%lo relocation
1764 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1765 }
1766
1767 // Every other architecture would use shouldAssumeDSOLocal in here, but
1768 // mips is special.
1769 // * In PIC code mips requires got loads even for local statics!
1770 // * To save on got entries, for local statics the got entry contains the
1771 // page and an additional add instruction takes care of the low bits.
1772 // * It is legal to access a hidden symbol with a non hidden undefined,
1773 // so one cannot guarantee that all access to a hidden symbol will know
1774 // it is hidden.
1775 // * Mips linkers don't support creating a page and a full got entry for
1776 // the same symbol.
1777 // * Given all that, we have to use a full got entry for hidden symbols :-(
1778 if (GV->hasLocalLinkage())
1779 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1780
1781 if (LargeGOT)
1782 return getAddrGlobalLargeGOT(
1783 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
1784 DAG.getEntryNode(),
1785 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1786
1787 return getAddrGlobal(
1788 N, SDLoc(N), Ty, DAG,
1789 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT,
1790 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1791 }
1792
lowerBlockAddress(SDValue Op,SelectionDAG & DAG) const1793 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1794 SelectionDAG &DAG) const {
1795 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1796 EVT Ty = Op.getValueType();
1797
1798 if (!isPositionIndependent() && !ABI.IsN64())
1799 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1800
1801 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1802 }
1803
1804 SDValue MipsTargetLowering::
lowerGlobalTLSAddress(SDValue Op,SelectionDAG & DAG) const1805 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1806 {
1807 // If the relocation model is PIC, use the General Dynamic TLS Model or
1808 // Local Dynamic TLS model, otherwise use the Initial Exec or
1809 // Local Exec TLS Model.
1810
1811 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1812 if (DAG.getTarget().Options.EmulatedTLS)
1813 return LowerToTLSEmulatedModel(GA, DAG);
1814
1815 SDLoc DL(GA);
1816 const GlobalValue *GV = GA->getGlobal();
1817 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1818
1819 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1820
1821 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1822 // General Dynamic and Local Dynamic TLS Model.
1823 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1824 : MipsII::MO_TLSGD;
1825
1826 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1827 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1828 getGlobalReg(DAG, PtrVT), TGA);
1829 unsigned PtrSize = PtrVT.getSizeInBits();
1830 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1831
1832 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1833
1834 ArgListTy Args;
1835 ArgListEntry Entry;
1836 Entry.Node = Argument;
1837 Entry.Ty = PtrTy;
1838 Args.push_back(Entry);
1839
1840 TargetLowering::CallLoweringInfo CLI(DAG);
1841 CLI.setDebugLoc(DL).setChain(DAG.getEntryNode())
1842 .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
1843 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1844
1845 SDValue Ret = CallResult.first;
1846
1847 if (model != TLSModel::LocalDynamic)
1848 return Ret;
1849
1850 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1851 MipsII::MO_DTPREL_HI);
1852 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1853 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1854 MipsII::MO_DTPREL_LO);
1855 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1856 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1857 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1858 }
1859
1860 SDValue Offset;
1861 if (model == TLSModel::InitialExec) {
1862 // Initial Exec TLS Model
1863 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1864 MipsII::MO_GOTTPREL);
1865 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1866 TGA);
1867 Offset = DAG.getLoad(PtrVT, DL,
1868 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1869 false, false, false, 0);
1870 } else {
1871 // Local Exec TLS Model
1872 assert(model == TLSModel::LocalExec);
1873 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1874 MipsII::MO_TPREL_HI);
1875 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1876 MipsII::MO_TPREL_LO);
1877 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1878 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1879 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1880 }
1881
1882 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1883 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1884 }
1885
1886 SDValue MipsTargetLowering::
lowerJumpTable(SDValue Op,SelectionDAG & DAG) const1887 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1888 {
1889 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1890 EVT Ty = Op.getValueType();
1891
1892 if (!isPositionIndependent() && !ABI.IsN64())
1893 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1894
1895 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1896 }
1897
1898 SDValue MipsTargetLowering::
lowerConstantPool(SDValue Op,SelectionDAG & DAG) const1899 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1900 {
1901 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1902 EVT Ty = Op.getValueType();
1903
1904 if (!isPositionIndependent() && !ABI.IsN64()) {
1905 const MipsTargetObjectFile *TLOF =
1906 static_cast<const MipsTargetObjectFile *>(
1907 getTargetMachine().getObjFileLowering());
1908
1909 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
1910 getTargetMachine()))
1911 // %gp_rel relocation
1912 return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1913
1914 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1915 }
1916
1917 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1918 }
1919
lowerVASTART(SDValue Op,SelectionDAG & DAG) const1920 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1921 MachineFunction &MF = DAG.getMachineFunction();
1922 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1923
1924 SDLoc DL(Op);
1925 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1926 getPointerTy(MF.getDataLayout()));
1927
1928 // vastart just stores the address of the VarArgsFrameIndex slot into the
1929 // memory location argument.
1930 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1931 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1932 MachinePointerInfo(SV), false, false, 0);
1933 }
1934
lowerVAARG(SDValue Op,SelectionDAG & DAG) const1935 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
1936 SDNode *Node = Op.getNode();
1937 EVT VT = Node->getValueType(0);
1938 SDValue Chain = Node->getOperand(0);
1939 SDValue VAListPtr = Node->getOperand(1);
1940 unsigned Align = Node->getConstantOperandVal(3);
1941 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1942 SDLoc DL(Node);
1943 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
1944
1945 SDValue VAListLoad =
1946 DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, VAListPtr,
1947 MachinePointerInfo(SV), false, false, false, 0);
1948 SDValue VAList = VAListLoad;
1949
1950 // Re-align the pointer if necessary.
1951 // It should only ever be necessary for 64-bit types on O32 since the minimum
1952 // argument alignment is the same as the maximum type alignment for N32/N64.
1953 //
1954 // FIXME: We currently align too often. The code generator doesn't notice
1955 // when the pointer is still aligned from the last va_arg (or pair of
1956 // va_args for the i64 on O32 case).
1957 if (Align > getMinStackArgumentAlignment()) {
1958 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
1959
1960 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1961 DAG.getConstant(Align - 1, DL, VAList.getValueType()));
1962
1963 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
1964 DAG.getConstant(-(int64_t)Align, DL,
1965 VAList.getValueType()));
1966 }
1967
1968 // Increment the pointer, VAList, to the next vaarg.
1969 auto &TD = DAG.getDataLayout();
1970 unsigned ArgSizeInBytes =
1971 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
1972 SDValue Tmp3 =
1973 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1974 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
1975 DL, VAList.getValueType()));
1976 // Store the incremented VAList to the legalized pointer
1977 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
1978 MachinePointerInfo(SV), false, false, 0);
1979
1980 // In big-endian mode we must adjust the pointer when the load size is smaller
1981 // than the argument slot size. We must also reduce the known alignment to
1982 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
1983 // the correct half of the slot, and reduce the alignment from 8 (slot
1984 // alignment) down to 4 (type alignment).
1985 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
1986 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
1987 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
1988 DAG.getIntPtrConstant(Adjustment, DL));
1989 }
1990 // Load the actual argument out of the pointer VAList
1991 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
1992 false, 0);
1993 }
1994
lowerFCOPYSIGN32(SDValue Op,SelectionDAG & DAG,bool HasExtractInsert)1995 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
1996 bool HasExtractInsert) {
1997 EVT TyX = Op.getOperand(0).getValueType();
1998 EVT TyY = Op.getOperand(1).getValueType();
1999 SDLoc DL(Op);
2000 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2001 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2002 SDValue Res;
2003
2004 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2005 // to i32.
2006 SDValue X = (TyX == MVT::f32) ?
2007 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2008 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2009 Const1);
2010 SDValue Y = (TyY == MVT::f32) ?
2011 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2012 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2013 Const1);
2014
2015 if (HasExtractInsert) {
2016 // ext E, Y, 31, 1 ; extract bit31 of Y
2017 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2018 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2019 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2020 } else {
2021 // sll SllX, X, 1
2022 // srl SrlX, SllX, 1
2023 // srl SrlY, Y, 31
2024 // sll SllY, SrlX, 31
2025 // or Or, SrlX, SllY
2026 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2027 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2028 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2029 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2030 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2031 }
2032
2033 if (TyX == MVT::f32)
2034 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2035
2036 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2037 Op.getOperand(0),
2038 DAG.getConstant(0, DL, MVT::i32));
2039 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2040 }
2041
lowerFCOPYSIGN64(SDValue Op,SelectionDAG & DAG,bool HasExtractInsert)2042 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
2043 bool HasExtractInsert) {
2044 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2045 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2046 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2047 SDLoc DL(Op);
2048 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2049
2050 // Bitcast to integer nodes.
2051 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2052 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2053
2054 if (HasExtractInsert) {
2055 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2056 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2057 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2058 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2059
2060 if (WidthX > WidthY)
2061 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2062 else if (WidthY > WidthX)
2063 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2064
2065 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2066 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2067 X);
2068 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2069 }
2070
2071 // (d)sll SllX, X, 1
2072 // (d)srl SrlX, SllX, 1
2073 // (d)srl SrlY, Y, width(Y)-1
2074 // (d)sll SllY, SrlX, width(Y)-1
2075 // or Or, SrlX, SllY
2076 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2077 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2078 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2079 DAG.getConstant(WidthY - 1, DL, MVT::i32));
2080
2081 if (WidthX > WidthY)
2082 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2083 else if (WidthY > WidthX)
2084 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2085
2086 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2087 DAG.getConstant(WidthX - 1, DL, MVT::i32));
2088 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2089 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2090 }
2091
2092 SDValue
lowerFCOPYSIGN(SDValue Op,SelectionDAG & DAG) const2093 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2094 if (Subtarget.isGP64bit())
2095 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2096
2097 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2098 }
2099
2100 SDValue MipsTargetLowering::
lowerFRAMEADDR(SDValue Op,SelectionDAG & DAG) const2101 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2102 // check the depth
2103 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2104 "Frame address can only be determined for current frame.");
2105
2106 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2107 MFI->setFrameAddressIsTaken(true);
2108 EVT VT = Op.getValueType();
2109 SDLoc DL(Op);
2110 SDValue FrameAddr = DAG.getCopyFromReg(
2111 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2112 return FrameAddr;
2113 }
2114
lowerRETURNADDR(SDValue Op,SelectionDAG & DAG) const2115 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2116 SelectionDAG &DAG) const {
2117 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2118 return SDValue();
2119
2120 // check the depth
2121 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2122 "Return address can be determined only for current frame.");
2123
2124 MachineFunction &MF = DAG.getMachineFunction();
2125 MachineFrameInfo *MFI = MF.getFrameInfo();
2126 MVT VT = Op.getSimpleValueType();
2127 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2128 MFI->setReturnAddressIsTaken(true);
2129
2130 // Return RA, which contains the return address. Mark it an implicit live-in.
2131 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2132 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2133 }
2134
2135 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2136 // generated from __builtin_eh_return (offset, handler)
2137 // The effect of this is to adjust the stack pointer by "offset"
2138 // and then branch to "handler".
lowerEH_RETURN(SDValue Op,SelectionDAG & DAG) const2139 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2140 const {
2141 MachineFunction &MF = DAG.getMachineFunction();
2142 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2143
2144 MipsFI->setCallsEhReturn();
2145 SDValue Chain = Op.getOperand(0);
2146 SDValue Offset = Op.getOperand(1);
2147 SDValue Handler = Op.getOperand(2);
2148 SDLoc DL(Op);
2149 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2150
2151 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2152 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2153 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2154 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2155 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2156 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2157 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2158 DAG.getRegister(OffsetReg, Ty),
2159 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2160 Chain.getValue(1));
2161 }
2162
lowerATOMIC_FENCE(SDValue Op,SelectionDAG & DAG) const2163 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2164 SelectionDAG &DAG) const {
2165 // FIXME: Need pseudo-fence for 'singlethread' fences
2166 // FIXME: Set SType for weaker fences where supported/appropriate.
2167 unsigned SType = 0;
2168 SDLoc DL(Op);
2169 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2170 DAG.getConstant(SType, DL, MVT::i32));
2171 }
2172
lowerShiftLeftParts(SDValue Op,SelectionDAG & DAG) const2173 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2174 SelectionDAG &DAG) const {
2175 SDLoc DL(Op);
2176 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2177
2178 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2179 SDValue Shamt = Op.getOperand(2);
2180 // if shamt < (VT.bits):
2181 // lo = (shl lo, shamt)
2182 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2183 // else:
2184 // lo = 0
2185 // hi = (shl lo, shamt[4:0])
2186 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2187 DAG.getConstant(-1, DL, MVT::i32));
2188 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2189 DAG.getConstant(1, DL, VT));
2190 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2191 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2192 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2193 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2194 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2195 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2196 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2197 DAG.getConstant(0, DL, VT), ShiftLeftLo);
2198 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2199
2200 SDValue Ops[2] = {Lo, Hi};
2201 return DAG.getMergeValues(Ops, DL);
2202 }
2203
lowerShiftRightParts(SDValue Op,SelectionDAG & DAG,bool IsSRA) const2204 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2205 bool IsSRA) const {
2206 SDLoc DL(Op);
2207 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2208 SDValue Shamt = Op.getOperand(2);
2209 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2210
2211 // if shamt < (VT.bits):
2212 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2213 // if isSRA:
2214 // hi = (sra hi, shamt)
2215 // else:
2216 // hi = (srl hi, shamt)
2217 // else:
2218 // if isSRA:
2219 // lo = (sra hi, shamt[4:0])
2220 // hi = (sra hi, 31)
2221 // else:
2222 // lo = (srl hi, shamt[4:0])
2223 // hi = 0
2224 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2225 DAG.getConstant(-1, DL, MVT::i32));
2226 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2227 DAG.getConstant(1, DL, VT));
2228 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2229 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2230 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2231 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2232 DL, VT, Hi, Shamt);
2233 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2234 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2235 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2236 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2237 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2238 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2239 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2240
2241 SDValue Ops[2] = {Lo, Hi};
2242 return DAG.getMergeValues(Ops, DL);
2243 }
2244
createLoadLR(unsigned Opc,SelectionDAG & DAG,LoadSDNode * LD,SDValue Chain,SDValue Src,unsigned Offset)2245 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2246 SDValue Chain, SDValue Src, unsigned Offset) {
2247 SDValue Ptr = LD->getBasePtr();
2248 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2249 EVT BasePtrVT = Ptr.getValueType();
2250 SDLoc DL(LD);
2251 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2252
2253 if (Offset)
2254 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2255 DAG.getConstant(Offset, DL, BasePtrVT));
2256
2257 SDValue Ops[] = { Chain, Ptr, Src };
2258 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2259 LD->getMemOperand());
2260 }
2261
2262 // Expand an unaligned 32 or 64-bit integer load node.
lowerLOAD(SDValue Op,SelectionDAG & DAG) const2263 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2264 LoadSDNode *LD = cast<LoadSDNode>(Op);
2265 EVT MemVT = LD->getMemoryVT();
2266
2267 if (Subtarget.systemSupportsUnalignedAccess())
2268 return Op;
2269
2270 // Return if load is aligned or if MemVT is neither i32 nor i64.
2271 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2272 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2273 return SDValue();
2274
2275 bool IsLittle = Subtarget.isLittle();
2276 EVT VT = Op.getValueType();
2277 ISD::LoadExtType ExtType = LD->getExtensionType();
2278 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2279
2280 assert((VT == MVT::i32) || (VT == MVT::i64));
2281
2282 // Expand
2283 // (set dst, (i64 (load baseptr)))
2284 // to
2285 // (set tmp, (ldl (add baseptr, 7), undef))
2286 // (set dst, (ldr baseptr, tmp))
2287 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2288 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2289 IsLittle ? 7 : 0);
2290 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2291 IsLittle ? 0 : 7);
2292 }
2293
2294 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2295 IsLittle ? 3 : 0);
2296 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2297 IsLittle ? 0 : 3);
2298
2299 // Expand
2300 // (set dst, (i32 (load baseptr))) or
2301 // (set dst, (i64 (sextload baseptr))) or
2302 // (set dst, (i64 (extload baseptr)))
2303 // to
2304 // (set tmp, (lwl (add baseptr, 3), undef))
2305 // (set dst, (lwr baseptr, tmp))
2306 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2307 (ExtType == ISD::EXTLOAD))
2308 return LWR;
2309
2310 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2311
2312 // Expand
2313 // (set dst, (i64 (zextload baseptr)))
2314 // to
2315 // (set tmp0, (lwl (add baseptr, 3), undef))
2316 // (set tmp1, (lwr baseptr, tmp0))
2317 // (set tmp2, (shl tmp1, 32))
2318 // (set dst, (srl tmp2, 32))
2319 SDLoc DL(LD);
2320 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2321 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2322 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2323 SDValue Ops[] = { SRL, LWR.getValue(1) };
2324 return DAG.getMergeValues(Ops, DL);
2325 }
2326
createStoreLR(unsigned Opc,SelectionDAG & DAG,StoreSDNode * SD,SDValue Chain,unsigned Offset)2327 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2328 SDValue Chain, unsigned Offset) {
2329 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2330 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2331 SDLoc DL(SD);
2332 SDVTList VTList = DAG.getVTList(MVT::Other);
2333
2334 if (Offset)
2335 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2336 DAG.getConstant(Offset, DL, BasePtrVT));
2337
2338 SDValue Ops[] = { Chain, Value, Ptr };
2339 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2340 SD->getMemOperand());
2341 }
2342
2343 // Expand an unaligned 32 or 64-bit integer store node.
lowerUnalignedIntStore(StoreSDNode * SD,SelectionDAG & DAG,bool IsLittle)2344 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2345 bool IsLittle) {
2346 SDValue Value = SD->getValue(), Chain = SD->getChain();
2347 EVT VT = Value.getValueType();
2348
2349 // Expand
2350 // (store val, baseptr) or
2351 // (truncstore val, baseptr)
2352 // to
2353 // (swl val, (add baseptr, 3))
2354 // (swr val, baseptr)
2355 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2356 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2357 IsLittle ? 3 : 0);
2358 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2359 }
2360
2361 assert(VT == MVT::i64);
2362
2363 // Expand
2364 // (store val, baseptr)
2365 // to
2366 // (sdl val, (add baseptr, 7))
2367 // (sdr val, baseptr)
2368 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2369 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2370 }
2371
2372 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
lowerFP_TO_SINT_STORE(StoreSDNode * SD,SelectionDAG & DAG)2373 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2374 SDValue Val = SD->getValue();
2375
2376 if (Val.getOpcode() != ISD::FP_TO_SINT)
2377 return SDValue();
2378
2379 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2380 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2381 Val.getOperand(0));
2382
2383 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2384 SD->getPointerInfo(), SD->isVolatile(),
2385 SD->isNonTemporal(), SD->getAlignment());
2386 }
2387
lowerSTORE(SDValue Op,SelectionDAG & DAG) const2388 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2389 StoreSDNode *SD = cast<StoreSDNode>(Op);
2390 EVT MemVT = SD->getMemoryVT();
2391
2392 // Lower unaligned integer stores.
2393 if (!Subtarget.systemSupportsUnalignedAccess() &&
2394 (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2395 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2396 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2397
2398 return lowerFP_TO_SINT_STORE(SD, DAG);
2399 }
2400
lowerADD(SDValue Op,SelectionDAG & DAG) const2401 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2402 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2403 || cast<ConstantSDNode>
2404 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2405 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2406 return SDValue();
2407
2408 // The pattern
2409 // (add (frameaddr 0), (frame_to_args_offset))
2410 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2411 // (add FrameObject, 0)
2412 // where FrameObject is a fixed StackObject with offset 0 which points to
2413 // the old stack pointer.
2414 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2415 EVT ValTy = Op->getValueType(0);
2416 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2417 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2418 SDLoc DL(Op);
2419 return DAG.getNode(ISD::ADD, DL, ValTy, InArgsAddr,
2420 DAG.getConstant(0, DL, ValTy));
2421 }
2422
lowerFP_TO_SINT(SDValue Op,SelectionDAG & DAG) const2423 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2424 SelectionDAG &DAG) const {
2425 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2426 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2427 Op.getOperand(0));
2428 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2429 }
2430
2431 //===----------------------------------------------------------------------===//
2432 // Calling Convention Implementation
2433 //===----------------------------------------------------------------------===//
2434
2435 //===----------------------------------------------------------------------===//
2436 // TODO: Implement a generic logic using tblgen that can support this.
2437 // Mips O32 ABI rules:
2438 // ---
2439 // i32 - Passed in A0, A1, A2, A3 and stack
2440 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2441 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2442 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2443 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2444 // not used, it must be shadowed. If only A3 is available, shadow it and
2445 // go to stack.
2446 //
2447 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2448 //===----------------------------------------------------------------------===//
2449
CC_MipsO32(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State,ArrayRef<MCPhysReg> F64Regs)2450 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2451 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2452 CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2453 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2454 State.getMachineFunction().getSubtarget());
2455
2456 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2457 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2458
2459 // Do not process byval args here.
2460 if (ArgFlags.isByVal())
2461 return true;
2462
2463 // Promote i8 and i16
2464 if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2465 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2466 LocVT = MVT::i32;
2467 if (ArgFlags.isSExt())
2468 LocInfo = CCValAssign::SExtUpper;
2469 else if (ArgFlags.isZExt())
2470 LocInfo = CCValAssign::ZExtUpper;
2471 else
2472 LocInfo = CCValAssign::AExtUpper;
2473 }
2474 }
2475
2476 // Promote i8 and i16
2477 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2478 LocVT = MVT::i32;
2479 if (ArgFlags.isSExt())
2480 LocInfo = CCValAssign::SExt;
2481 else if (ArgFlags.isZExt())
2482 LocInfo = CCValAssign::ZExt;
2483 else
2484 LocInfo = CCValAssign::AExt;
2485 }
2486
2487 unsigned Reg;
2488
2489 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2490 // is true: function is vararg, argument is 3rd or higher, there is previous
2491 // argument which is not f32 or f64.
2492 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2493 State.getFirstUnallocated(F32Regs) != ValNo;
2494 unsigned OrigAlign = ArgFlags.getOrigAlign();
2495 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2496
2497 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2498 Reg = State.AllocateReg(IntRegs);
2499 // If this is the first part of an i64 arg,
2500 // the allocated register must be either A0 or A2.
2501 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2502 Reg = State.AllocateReg(IntRegs);
2503 LocVT = MVT::i32;
2504 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2505 // Allocate int register and shadow next int register. If first
2506 // available register is Mips::A1 or Mips::A3, shadow it too.
2507 Reg = State.AllocateReg(IntRegs);
2508 if (Reg == Mips::A1 || Reg == Mips::A3)
2509 Reg = State.AllocateReg(IntRegs);
2510 State.AllocateReg(IntRegs);
2511 LocVT = MVT::i32;
2512 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2513 // we are guaranteed to find an available float register
2514 if (ValVT == MVT::f32) {
2515 Reg = State.AllocateReg(F32Regs);
2516 // Shadow int register
2517 State.AllocateReg(IntRegs);
2518 } else {
2519 Reg = State.AllocateReg(F64Regs);
2520 // Shadow int registers
2521 unsigned Reg2 = State.AllocateReg(IntRegs);
2522 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2523 State.AllocateReg(IntRegs);
2524 State.AllocateReg(IntRegs);
2525 }
2526 } else
2527 llvm_unreachable("Cannot handle this ValVT.");
2528
2529 if (!Reg) {
2530 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2531 OrigAlign);
2532 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2533 } else
2534 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2535
2536 return false;
2537 }
2538
CC_MipsO32_FP32(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)2539 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2540 MVT LocVT, CCValAssign::LocInfo LocInfo,
2541 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2542 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2543
2544 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2545 }
2546
CC_MipsO32_FP64(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)2547 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2548 MVT LocVT, CCValAssign::LocInfo LocInfo,
2549 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2550 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2551
2552 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2553 }
2554
2555 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2556 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2557 CCState &State) LLVM_ATTRIBUTE_UNUSED;
2558
2559 #include "MipsGenCallingConv.inc"
2560
2561 //===----------------------------------------------------------------------===//
2562 // Call Calling Convention Implementation
2563 //===----------------------------------------------------------------------===//
2564
2565 // Return next O32 integer argument register.
getNextIntArgReg(unsigned Reg)2566 static unsigned getNextIntArgReg(unsigned Reg) {
2567 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2568 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2569 }
2570
passArgOnStack(SDValue StackPtr,unsigned Offset,SDValue Chain,SDValue Arg,const SDLoc & DL,bool IsTailCall,SelectionDAG & DAG) const2571 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2572 SDValue Chain, SDValue Arg,
2573 const SDLoc &DL, bool IsTailCall,
2574 SelectionDAG &DAG) const {
2575 if (!IsTailCall) {
2576 SDValue PtrOff =
2577 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2578 DAG.getIntPtrConstant(Offset, DL));
2579 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2580 false, 0);
2581 }
2582
2583 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2584 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2585 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2586 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2587 /*isVolatile=*/ true, false, 0);
2588 }
2589
2590 void MipsTargetLowering::
getOpndList(SmallVectorImpl<SDValue> & Ops,std::deque<std::pair<unsigned,SDValue>> & RegsToPass,bool IsPICCall,bool GlobalOrExternal,bool InternalLinkage,bool IsCallReloc,CallLoweringInfo & CLI,SDValue Callee,SDValue Chain) const2591 getOpndList(SmallVectorImpl<SDValue> &Ops,
2592 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2593 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2594 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2595 SDValue Chain) const {
2596 // Insert node "GP copy globalreg" before call to function.
2597 //
2598 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2599 // in PIC mode) allow symbols to be resolved via lazy binding.
2600 // The lazy binding stub requires GP to point to the GOT.
2601 // Note that we don't need GP to point to the GOT for indirect calls
2602 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2603 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2604 // used for the function (that is, Mips linker doesn't generate lazy binding
2605 // stub for a function whose address is taken in the program).
2606 if (IsPICCall && !InternalLinkage && IsCallReloc) {
2607 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2608 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2609 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2610 }
2611
2612 // Build a sequence of copy-to-reg nodes chained together with token
2613 // chain and flag operands which copy the outgoing args into registers.
2614 // The InFlag in necessary since all emitted instructions must be
2615 // stuck together.
2616 SDValue InFlag;
2617
2618 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2619 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2620 RegsToPass[i].second, InFlag);
2621 InFlag = Chain.getValue(1);
2622 }
2623
2624 // Add argument registers to the end of the list so that they are
2625 // known live into the call.
2626 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2627 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2628 RegsToPass[i].second.getValueType()));
2629
2630 // Add a register mask operand representing the call-preserved registers.
2631 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2632 const uint32_t *Mask =
2633 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
2634 assert(Mask && "Missing call preserved mask for calling convention");
2635 if (Subtarget.inMips16HardFloat()) {
2636 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2637 llvm::StringRef Sym = G->getGlobal()->getName();
2638 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2639 if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2640 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2641 }
2642 }
2643 }
2644 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2645
2646 if (InFlag.getNode())
2647 Ops.push_back(InFlag);
2648 }
2649
2650 /// LowerCall - functions arguments are copied from virtual regs to
2651 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2652 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const2653 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2654 SmallVectorImpl<SDValue> &InVals) const {
2655 SelectionDAG &DAG = CLI.DAG;
2656 SDLoc DL = CLI.DL;
2657 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2658 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2659 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2660 SDValue Chain = CLI.Chain;
2661 SDValue Callee = CLI.Callee;
2662 bool &IsTailCall = CLI.IsTailCall;
2663 CallingConv::ID CallConv = CLI.CallConv;
2664 bool IsVarArg = CLI.IsVarArg;
2665
2666 MachineFunction &MF = DAG.getMachineFunction();
2667 MachineFrameInfo *MFI = MF.getFrameInfo();
2668 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
2669 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2670 bool IsPIC = isPositionIndependent();
2671
2672 // Analyze operands of the call, assigning locations to each operand.
2673 SmallVector<CCValAssign, 16> ArgLocs;
2674 MipsCCState CCInfo(
2675 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2676 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
2677
2678 // Allocate the reserved argument area. It seems strange to do this from the
2679 // caller side but removing it breaks the frame size calculation.
2680 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2681
2682 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode());
2683
2684 // Get a count of how many bytes are to be pushed on the stack.
2685 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2686
2687 // Check if it's really possible to do a tail call.
2688 if (IsTailCall)
2689 IsTailCall = isEligibleForTailCallOptimization(
2690 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
2691
2692 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2693 report_fatal_error("failed to perform tail call elimination on a call "
2694 "site marked musttail");
2695
2696 if (IsTailCall)
2697 ++NumTailCalls;
2698
2699 // Chain is the output chain of the last Load/Store or CopyToReg node.
2700 // ByValChain is the output chain of the last Memcpy node created for copying
2701 // byval arguments to the stack.
2702 unsigned StackAlignment = TFL->getStackAlignment();
2703 NextStackOffset = alignTo(NextStackOffset, StackAlignment);
2704 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
2705
2706 if (!IsTailCall)
2707 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2708
2709 SDValue StackPtr =
2710 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
2711 getPointerTy(DAG.getDataLayout()));
2712
2713 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2714 SmallVector<SDValue, 8> MemOpChains;
2715
2716 CCInfo.rewindByValRegsInfo();
2717
2718 // Walk the register/memloc assignments, inserting copies/loads.
2719 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2720 SDValue Arg = OutVals[i];
2721 CCValAssign &VA = ArgLocs[i];
2722 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2723 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2724 bool UseUpperBits = false;
2725
2726 // ByVal Arg.
2727 if (Flags.isByVal()) {
2728 unsigned FirstByValReg, LastByValReg;
2729 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2730 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2731
2732 assert(Flags.getByValSize() &&
2733 "ByVal args of size 0 should have been ignored by front-end.");
2734 assert(ByValIdx < CCInfo.getInRegsParamsCount());
2735 assert(!IsTailCall &&
2736 "Do not tail-call optimize if there is a byval argument.");
2737 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2738 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
2739 VA);
2740 CCInfo.nextInRegsParam();
2741 continue;
2742 }
2743
2744 // Promote the value if needed.
2745 switch (VA.getLocInfo()) {
2746 default:
2747 llvm_unreachable("Unknown loc info!");
2748 case CCValAssign::Full:
2749 if (VA.isRegLoc()) {
2750 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2751 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
2752 (ValVT == MVT::i64 && LocVT == MVT::f64))
2753 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2754 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2755 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2756 Arg, DAG.getConstant(0, DL, MVT::i32));
2757 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2758 Arg, DAG.getConstant(1, DL, MVT::i32));
2759 if (!Subtarget.isLittle())
2760 std::swap(Lo, Hi);
2761 unsigned LocRegLo = VA.getLocReg();
2762 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2763 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2764 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2765 continue;
2766 }
2767 }
2768 break;
2769 case CCValAssign::BCvt:
2770 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2771 break;
2772 case CCValAssign::SExtUpper:
2773 UseUpperBits = true;
2774 // Fallthrough
2775 case CCValAssign::SExt:
2776 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2777 break;
2778 case CCValAssign::ZExtUpper:
2779 UseUpperBits = true;
2780 // Fallthrough
2781 case CCValAssign::ZExt:
2782 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2783 break;
2784 case CCValAssign::AExtUpper:
2785 UseUpperBits = true;
2786 // Fallthrough
2787 case CCValAssign::AExt:
2788 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2789 break;
2790 }
2791
2792 if (UseUpperBits) {
2793 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
2794 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2795 Arg = DAG.getNode(
2796 ISD::SHL, DL, VA.getLocVT(), Arg,
2797 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2798 }
2799
2800 // Arguments that can be passed on register must be kept at
2801 // RegsToPass vector
2802 if (VA.isRegLoc()) {
2803 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2804 continue;
2805 }
2806
2807 // Register can't get to this point...
2808 assert(VA.isMemLoc());
2809
2810 // emit ISD::STORE whichs stores the
2811 // parameter value to a stack Location
2812 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2813 Chain, Arg, DL, IsTailCall, DAG));
2814 }
2815
2816 // Transform all store nodes into one single node because all store
2817 // nodes are independent of each other.
2818 if (!MemOpChains.empty())
2819 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2820
2821 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2822 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2823 // node so that legalize doesn't hack it.
2824 bool IsPICCall = (ABI.IsN64() || IsPIC); // true if calls are translated to
2825 // jalr $25
2826 bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false;
2827 SDValue CalleeLo;
2828 EVT Ty = Callee.getValueType();
2829
2830 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2831 if (IsPICCall) {
2832 const GlobalValue *Val = G->getGlobal();
2833 InternalLinkage = Val->hasInternalLinkage();
2834
2835 if (InternalLinkage)
2836 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
2837 else if (LargeGOT) {
2838 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2839 MipsII::MO_CALL_LO16, Chain,
2840 FuncInfo->callPtrInfo(Val));
2841 IsCallReloc = true;
2842 } else {
2843 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2844 FuncInfo->callPtrInfo(Val));
2845 IsCallReloc = true;
2846 }
2847 } else
2848 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
2849 getPointerTy(DAG.getDataLayout()), 0,
2850 MipsII::MO_NO_FLAG);
2851 GlobalOrExternal = true;
2852 }
2853 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2854 const char *Sym = S->getSymbol();
2855
2856 if (!ABI.IsN64() && !IsPIC) // !N64 && static
2857 Callee = DAG.getTargetExternalSymbol(
2858 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
2859 else if (LargeGOT) {
2860 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2861 MipsII::MO_CALL_LO16, Chain,
2862 FuncInfo->callPtrInfo(Sym));
2863 IsCallReloc = true;
2864 } else { // N64 || PIC
2865 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2866 FuncInfo->callPtrInfo(Sym));
2867 IsCallReloc = true;
2868 }
2869
2870 GlobalOrExternal = true;
2871 }
2872
2873 SmallVector<SDValue, 8> Ops(1, Chain);
2874 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2875
2876 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2877 IsCallReloc, CLI, Callee, Chain);
2878
2879 if (IsTailCall)
2880 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
2881
2882 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
2883 SDValue InFlag = Chain.getValue(1);
2884
2885 // Create the CALLSEQ_END node.
2886 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2887 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2888 InFlag = Chain.getValue(1);
2889
2890 // Handle result values, copying them out of physregs into vregs that we
2891 // return.
2892 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2893 InVals, CLI);
2894 }
2895
2896 /// LowerCallResult - Lower the result values of a call into the
2897 /// appropriate copies out of appropriate physical registers.
LowerCallResult(SDValue Chain,SDValue InFlag,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals,TargetLowering::CallLoweringInfo & CLI) const2898 SDValue MipsTargetLowering::LowerCallResult(
2899 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2900 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2901 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
2902 TargetLowering::CallLoweringInfo &CLI) const {
2903 // Assign locations to each value returned by this call.
2904 SmallVector<CCValAssign, 16> RVLocs;
2905 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2906 *DAG.getContext());
2907 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI);
2908
2909 // Copy all of the result registers out of their specified physreg.
2910 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2911 CCValAssign &VA = RVLocs[i];
2912 assert(VA.isRegLoc() && "Can only return in registers!");
2913
2914 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2915 RVLocs[i].getLocVT(), InFlag);
2916 Chain = Val.getValue(1);
2917 InFlag = Val.getValue(2);
2918
2919 if (VA.isUpperBitsInLoc()) {
2920 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
2921 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2922 unsigned Shift =
2923 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2924 Val = DAG.getNode(
2925 Shift, DL, VA.getLocVT(), Val,
2926 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2927 }
2928
2929 switch (VA.getLocInfo()) {
2930 default:
2931 llvm_unreachable("Unknown loc info!");
2932 case CCValAssign::Full:
2933 break;
2934 case CCValAssign::BCvt:
2935 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2936 break;
2937 case CCValAssign::AExt:
2938 case CCValAssign::AExtUpper:
2939 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2940 break;
2941 case CCValAssign::ZExt:
2942 case CCValAssign::ZExtUpper:
2943 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2944 DAG.getValueType(VA.getValVT()));
2945 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2946 break;
2947 case CCValAssign::SExt:
2948 case CCValAssign::SExtUpper:
2949 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2950 DAG.getValueType(VA.getValVT()));
2951 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2952 break;
2953 }
2954
2955 InVals.push_back(Val);
2956 }
2957
2958 return Chain;
2959 }
2960
UnpackFromArgumentSlot(SDValue Val,const CCValAssign & VA,EVT ArgVT,const SDLoc & DL,SelectionDAG & DAG)2961 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
2962 EVT ArgVT, const SDLoc &DL,
2963 SelectionDAG &DAG) {
2964 MVT LocVT = VA.getLocVT();
2965 EVT ValVT = VA.getValVT();
2966
2967 // Shift into the upper bits if necessary.
2968 switch (VA.getLocInfo()) {
2969 default:
2970 break;
2971 case CCValAssign::AExtUpper:
2972 case CCValAssign::SExtUpper:
2973 case CCValAssign::ZExtUpper: {
2974 unsigned ValSizeInBits = ArgVT.getSizeInBits();
2975 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2976 unsigned Opcode =
2977 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2978 Val = DAG.getNode(
2979 Opcode, DL, VA.getLocVT(), Val,
2980 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2981 break;
2982 }
2983 }
2984
2985 // If this is an value smaller than the argument slot size (32-bit for O32,
2986 // 64-bit for N32/N64), it has been promoted in some way to the argument slot
2987 // size. Extract the value and insert any appropriate assertions regarding
2988 // sign/zero extension.
2989 switch (VA.getLocInfo()) {
2990 default:
2991 llvm_unreachable("Unknown loc info!");
2992 case CCValAssign::Full:
2993 break;
2994 case CCValAssign::AExtUpper:
2995 case CCValAssign::AExt:
2996 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2997 break;
2998 case CCValAssign::SExtUpper:
2999 case CCValAssign::SExt:
3000 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3001 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3002 break;
3003 case CCValAssign::ZExtUpper:
3004 case CCValAssign::ZExt:
3005 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3006 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3007 break;
3008 case CCValAssign::BCvt:
3009 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3010 break;
3011 }
3012
3013 return Val;
3014 }
3015
3016 //===----------------------------------------------------------------------===//
3017 // Formal Arguments Calling Convention Implementation
3018 //===----------------------------------------------------------------------===//
3019 /// LowerFormalArguments - transform physical registers into virtual registers
3020 /// and generate load operations for arguments places on the stack.
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const3021 SDValue MipsTargetLowering::LowerFormalArguments(
3022 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3023 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3024 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3025 MachineFunction &MF = DAG.getMachineFunction();
3026 MachineFrameInfo *MFI = MF.getFrameInfo();
3027 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3028
3029 MipsFI->setVarArgsFrameIndex(0);
3030
3031 // Used with vargs to acumulate store chains.
3032 std::vector<SDValue> OutChains;
3033
3034 // Assign locations to all of the incoming arguments.
3035 SmallVector<CCValAssign, 16> ArgLocs;
3036 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3037 *DAG.getContext());
3038 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
3039 const Function *Func = DAG.getMachineFunction().getFunction();
3040 Function::const_arg_iterator FuncArg = Func->arg_begin();
3041
3042 if (Func->hasFnAttribute("interrupt") && !Func->arg_empty())
3043 report_fatal_error(
3044 "Functions with the interrupt attribute cannot have arguments!");
3045
3046 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3047 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3048 CCInfo.getInRegsParamsCount() > 0);
3049
3050 unsigned CurArgIdx = 0;
3051 CCInfo.rewindByValRegsInfo();
3052
3053 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3054 CCValAssign &VA = ArgLocs[i];
3055 if (Ins[i].isOrigArg()) {
3056 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
3057 CurArgIdx = Ins[i].getOrigArgIndex();
3058 }
3059 EVT ValVT = VA.getValVT();
3060 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3061 bool IsRegLoc = VA.isRegLoc();
3062
3063 if (Flags.isByVal()) {
3064 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
3065 unsigned FirstByValReg, LastByValReg;
3066 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3067 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3068
3069 assert(Flags.getByValSize() &&
3070 "ByVal args of size 0 should have been ignored by front-end.");
3071 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3072 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3073 FirstByValReg, LastByValReg, VA, CCInfo);
3074 CCInfo.nextInRegsParam();
3075 continue;
3076 }
3077
3078 // Arguments stored on registers
3079 if (IsRegLoc) {
3080 MVT RegVT = VA.getLocVT();
3081 unsigned ArgReg = VA.getLocReg();
3082 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3083
3084 // Transform the arguments stored on
3085 // physical registers into virtual ones
3086 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3087 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3088
3089 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3090
3091 // Handle floating point arguments passed in integer registers and
3092 // long double arguments passed in floating point registers.
3093 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3094 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3095 (RegVT == MVT::f64 && ValVT == MVT::i64))
3096 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3097 else if (ABI.IsO32() && RegVT == MVT::i32 &&
3098 ValVT == MVT::f64) {
3099 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3100 getNextIntArgReg(ArgReg), RC);
3101 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3102 if (!Subtarget.isLittle())
3103 std::swap(ArgValue, ArgValue2);
3104 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3105 ArgValue, ArgValue2);
3106 }
3107
3108 InVals.push_back(ArgValue);
3109 } else { // VA.isRegLoc()
3110 MVT LocVT = VA.getLocVT();
3111
3112 if (ABI.IsO32()) {
3113 // We ought to be able to use LocVT directly but O32 sets it to i32
3114 // when allocating floating point values to integer registers.
3115 // This shouldn't influence how we load the value into registers unless
3116 // we are targeting softfloat.
3117 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
3118 LocVT = VA.getValVT();
3119 }
3120
3121 // sanity check
3122 assert(VA.isMemLoc());
3123
3124 // The stack pointer offset is relative to the caller stack frame.
3125 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
3126 VA.getLocMemOffset(), true);
3127
3128 // Create load nodes to retrieve arguments from the stack
3129 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3130 SDValue ArgValue = DAG.getLoad(
3131 LocVT, DL, Chain, FIN,
3132 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3133 false, false, false, 0);
3134 OutChains.push_back(ArgValue.getValue(1));
3135
3136 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3137
3138 InVals.push_back(ArgValue);
3139 }
3140 }
3141
3142 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3143 // The mips ABIs for returning structs by value requires that we copy
3144 // the sret argument into $v0 for the return. Save the argument into
3145 // a virtual register so that we can access it from the return points.
3146 if (Ins[i].Flags.isSRet()) {
3147 unsigned Reg = MipsFI->getSRetReturnReg();
3148 if (!Reg) {
3149 Reg = MF.getRegInfo().createVirtualRegister(
3150 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3151 MipsFI->setSRetReturnReg(Reg);
3152 }
3153 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3154 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3155 break;
3156 }
3157 }
3158
3159 if (IsVarArg)
3160 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3161
3162 // All stores are grouped in one node to allow the matching between
3163 // the size of Ins and InVals. This only happens when on varg functions
3164 if (!OutChains.empty()) {
3165 OutChains.push_back(Chain);
3166 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3167 }
3168
3169 return Chain;
3170 }
3171
3172 //===----------------------------------------------------------------------===//
3173 // Return Value Calling Convention Implementation
3174 //===----------------------------------------------------------------------===//
3175
3176 bool
CanLowerReturn(CallingConv::ID CallConv,MachineFunction & MF,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,LLVMContext & Context) const3177 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3178 MachineFunction &MF, bool IsVarArg,
3179 const SmallVectorImpl<ISD::OutputArg> &Outs,
3180 LLVMContext &Context) const {
3181 SmallVector<CCValAssign, 16> RVLocs;
3182 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3183 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3184 }
3185
3186 bool
shouldSignExtendTypeInLibCall(EVT Type,bool IsSigned) const3187 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3188 if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) {
3189 if (Type == MVT::i32)
3190 return true;
3191 }
3192 return IsSigned;
3193 }
3194
3195 SDValue
LowerInterruptReturn(SmallVectorImpl<SDValue> & RetOps,const SDLoc & DL,SelectionDAG & DAG) const3196 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3197 const SDLoc &DL,
3198 SelectionDAG &DAG) const {
3199
3200 MachineFunction &MF = DAG.getMachineFunction();
3201 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3202
3203 MipsFI->setISR();
3204
3205 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3206 }
3207
3208 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & DL,SelectionDAG & DAG) const3209 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3210 bool IsVarArg,
3211 const SmallVectorImpl<ISD::OutputArg> &Outs,
3212 const SmallVectorImpl<SDValue> &OutVals,
3213 const SDLoc &DL, SelectionDAG &DAG) const {
3214 // CCValAssign - represent the assignment of
3215 // the return value to a location
3216 SmallVector<CCValAssign, 16> RVLocs;
3217 MachineFunction &MF = DAG.getMachineFunction();
3218
3219 // CCState - Info about the registers and stack slot.
3220 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3221
3222 // Analyze return values.
3223 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3224
3225 SDValue Flag;
3226 SmallVector<SDValue, 4> RetOps(1, Chain);
3227
3228 // Copy the result values into the output registers.
3229 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3230 SDValue Val = OutVals[i];
3231 CCValAssign &VA = RVLocs[i];
3232 assert(VA.isRegLoc() && "Can only return in registers!");
3233 bool UseUpperBits = false;
3234
3235 switch (VA.getLocInfo()) {
3236 default:
3237 llvm_unreachable("Unknown loc info!");
3238 case CCValAssign::Full:
3239 break;
3240 case CCValAssign::BCvt:
3241 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3242 break;
3243 case CCValAssign::AExtUpper:
3244 UseUpperBits = true;
3245 // Fallthrough
3246 case CCValAssign::AExt:
3247 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3248 break;
3249 case CCValAssign::ZExtUpper:
3250 UseUpperBits = true;
3251 // Fallthrough
3252 case CCValAssign::ZExt:
3253 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3254 break;
3255 case CCValAssign::SExtUpper:
3256 UseUpperBits = true;
3257 // Fallthrough
3258 case CCValAssign::SExt:
3259 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3260 break;
3261 }
3262
3263 if (UseUpperBits) {
3264 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3265 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3266 Val = DAG.getNode(
3267 ISD::SHL, DL, VA.getLocVT(), Val,
3268 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3269 }
3270
3271 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3272
3273 // Guarantee that all emitted copies are stuck together with flags.
3274 Flag = Chain.getValue(1);
3275 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3276 }
3277
3278 // The mips ABIs for returning structs by value requires that we copy
3279 // the sret argument into $v0 for the return. We saved the argument into
3280 // a virtual register in the entry block, so now we copy the value out
3281 // and into $v0.
3282 if (MF.getFunction()->hasStructRetAttr()) {
3283 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3284 unsigned Reg = MipsFI->getSRetReturnReg();
3285
3286 if (!Reg)
3287 llvm_unreachable("sret virtual register not created in the entry block");
3288 SDValue Val =
3289 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3290 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3291
3292 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3293 Flag = Chain.getValue(1);
3294 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3295 }
3296
3297 RetOps[0] = Chain; // Update chain.
3298
3299 // Add the flag if we have it.
3300 if (Flag.getNode())
3301 RetOps.push_back(Flag);
3302
3303 // ISRs must use "eret".
3304 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt"))
3305 return LowerInterruptReturn(RetOps, DL, DAG);
3306
3307 // Standard return on Mips is a "jr $ra"
3308 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3309 }
3310
3311 //===----------------------------------------------------------------------===//
3312 // Mips Inline Assembly Support
3313 //===----------------------------------------------------------------------===//
3314
3315 /// getConstraintType - Given a constraint letter, return the type of
3316 /// constraint it is for this target.
3317 MipsTargetLowering::ConstraintType
getConstraintType(StringRef Constraint) const3318 MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3319 // Mips specific constraints
3320 // GCC config/mips/constraints.md
3321 //
3322 // 'd' : An address register. Equivalent to r
3323 // unless generating MIPS16 code.
3324 // 'y' : Equivalent to r; retained for
3325 // backwards compatibility.
3326 // 'c' : A register suitable for use in an indirect
3327 // jump. This will always be $25 for -mabicalls.
3328 // 'l' : The lo register. 1 word storage.
3329 // 'x' : The hilo register pair. Double word storage.
3330 if (Constraint.size() == 1) {
3331 switch (Constraint[0]) {
3332 default : break;
3333 case 'd':
3334 case 'y':
3335 case 'f':
3336 case 'c':
3337 case 'l':
3338 case 'x':
3339 return C_RegisterClass;
3340 case 'R':
3341 return C_Memory;
3342 }
3343 }
3344
3345 if (Constraint == "ZC")
3346 return C_Memory;
3347
3348 return TargetLowering::getConstraintType(Constraint);
3349 }
3350
3351 /// Examine constraint type and operand type and determine a weight value.
3352 /// This object must already have been set up with the operand type
3353 /// and the current alternative constraint selected.
3354 TargetLowering::ConstraintWeight
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const3355 MipsTargetLowering::getSingleConstraintMatchWeight(
3356 AsmOperandInfo &info, const char *constraint) const {
3357 ConstraintWeight weight = CW_Invalid;
3358 Value *CallOperandVal = info.CallOperandVal;
3359 // If we don't have a value, we can't do a match,
3360 // but allow it at the lowest weight.
3361 if (!CallOperandVal)
3362 return CW_Default;
3363 Type *type = CallOperandVal->getType();
3364 // Look at the constraint type.
3365 switch (*constraint) {
3366 default:
3367 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3368 break;
3369 case 'd':
3370 case 'y':
3371 if (type->isIntegerTy())
3372 weight = CW_Register;
3373 break;
3374 case 'f': // FPU or MSA register
3375 if (Subtarget.hasMSA() && type->isVectorTy() &&
3376 cast<VectorType>(type)->getBitWidth() == 128)
3377 weight = CW_Register;
3378 else if (type->isFloatTy())
3379 weight = CW_Register;
3380 break;
3381 case 'c': // $25 for indirect jumps
3382 case 'l': // lo register
3383 case 'x': // hilo register pair
3384 if (type->isIntegerTy())
3385 weight = CW_SpecificReg;
3386 break;
3387 case 'I': // signed 16 bit immediate
3388 case 'J': // integer zero
3389 case 'K': // unsigned 16 bit immediate
3390 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3391 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3392 case 'O': // signed 15 bit immediate (+- 16383)
3393 case 'P': // immediate in the range of 65535 to 1 (inclusive)
3394 if (isa<ConstantInt>(CallOperandVal))
3395 weight = CW_Constant;
3396 break;
3397 case 'R':
3398 weight = CW_Memory;
3399 break;
3400 }
3401 return weight;
3402 }
3403
3404 /// This is a helper function to parse a physical register string and split it
3405 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3406 /// that is returned indicates whether parsing was successful. The second flag
3407 /// is true if the numeric part exists.
parsePhysicalReg(StringRef C,StringRef & Prefix,unsigned long long & Reg)3408 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3409 unsigned long long &Reg) {
3410 if (C.front() != '{' || C.back() != '}')
3411 return std::make_pair(false, false);
3412
3413 // Search for the first numeric character.
3414 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3415 I = std::find_if(B, E, isdigit);
3416
3417 Prefix = StringRef(B, I - B);
3418
3419 // The second flag is set to false if no numeric characters were found.
3420 if (I == E)
3421 return std::make_pair(true, false);
3422
3423 // Parse the numeric characters.
3424 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3425 true);
3426 }
3427
3428 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
parseRegForInlineAsmConstraint(StringRef C,MVT VT) const3429 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3430 const TargetRegisterInfo *TRI =
3431 Subtarget.getRegisterInfo();
3432 const TargetRegisterClass *RC;
3433 StringRef Prefix;
3434 unsigned long long Reg;
3435
3436 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3437
3438 if (!R.first)
3439 return std::make_pair(0U, nullptr);
3440
3441 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3442 // No numeric characters follow "hi" or "lo".
3443 if (R.second)
3444 return std::make_pair(0U, nullptr);
3445
3446 RC = TRI->getRegClass(Prefix == "hi" ?
3447 Mips::HI32RegClassID : Mips::LO32RegClassID);
3448 return std::make_pair(*(RC->begin()), RC);
3449 } else if (Prefix.startswith("$msa")) {
3450 // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3451
3452 // No numeric characters follow the name.
3453 if (R.second)
3454 return std::make_pair(0U, nullptr);
3455
3456 Reg = StringSwitch<unsigned long long>(Prefix)
3457 .Case("$msair", Mips::MSAIR)
3458 .Case("$msacsr", Mips::MSACSR)
3459 .Case("$msaaccess", Mips::MSAAccess)
3460 .Case("$msasave", Mips::MSASave)
3461 .Case("$msamodify", Mips::MSAModify)
3462 .Case("$msarequest", Mips::MSARequest)
3463 .Case("$msamap", Mips::MSAMap)
3464 .Case("$msaunmap", Mips::MSAUnmap)
3465 .Default(0);
3466
3467 if (!Reg)
3468 return std::make_pair(0U, nullptr);
3469
3470 RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3471 return std::make_pair(Reg, RC);
3472 }
3473
3474 if (!R.second)
3475 return std::make_pair(0U, nullptr);
3476
3477 if (Prefix == "$f") { // Parse $f0-$f31.
3478 // If the size of FP registers is 64-bit or Reg is an even number, select
3479 // the 64-bit register class. Otherwise, select the 32-bit register class.
3480 if (VT == MVT::Other)
3481 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3482
3483 RC = getRegClassFor(VT);
3484
3485 if (RC == &Mips::AFGR64RegClass) {
3486 assert(Reg % 2 == 0);
3487 Reg >>= 1;
3488 }
3489 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3490 RC = TRI->getRegClass(Mips::FCCRegClassID);
3491 else if (Prefix == "$w") { // Parse $w0-$w31.
3492 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3493 } else { // Parse $0-$31.
3494 assert(Prefix == "$");
3495 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3496 }
3497
3498 assert(Reg < RC->getNumRegs());
3499 return std::make_pair(*(RC->begin() + Reg), RC);
3500 }
3501
3502 /// Given a register class constraint, like 'r', if this corresponds directly
3503 /// to an LLVM register class, return a register of 0 and the register class
3504 /// pointer.
3505 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,StringRef Constraint,MVT VT) const3506 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3507 StringRef Constraint,
3508 MVT VT) const {
3509 if (Constraint.size() == 1) {
3510 switch (Constraint[0]) {
3511 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3512 case 'y': // Same as 'r'. Exists for compatibility.
3513 case 'r':
3514 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3515 if (Subtarget.inMips16Mode())
3516 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3517 return std::make_pair(0U, &Mips::GPR32RegClass);
3518 }
3519 if (VT == MVT::i64 && !Subtarget.isGP64bit())
3520 return std::make_pair(0U, &Mips::GPR32RegClass);
3521 if (VT == MVT::i64 && Subtarget.isGP64bit())
3522 return std::make_pair(0U, &Mips::GPR64RegClass);
3523 // This will generate an error message
3524 return std::make_pair(0U, nullptr);
3525 case 'f': // FPU or MSA register
3526 if (VT == MVT::v16i8)
3527 return std::make_pair(0U, &Mips::MSA128BRegClass);
3528 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3529 return std::make_pair(0U, &Mips::MSA128HRegClass);
3530 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3531 return std::make_pair(0U, &Mips::MSA128WRegClass);
3532 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3533 return std::make_pair(0U, &Mips::MSA128DRegClass);
3534 else if (VT == MVT::f32)
3535 return std::make_pair(0U, &Mips::FGR32RegClass);
3536 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3537 if (Subtarget.isFP64bit())
3538 return std::make_pair(0U, &Mips::FGR64RegClass);
3539 return std::make_pair(0U, &Mips::AFGR64RegClass);
3540 }
3541 break;
3542 case 'c': // register suitable for indirect jump
3543 if (VT == MVT::i32)
3544 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3545 assert(VT == MVT::i64 && "Unexpected type.");
3546 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3547 case 'l': // register suitable for indirect jump
3548 if (VT == MVT::i32)
3549 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3550 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3551 case 'x': // register suitable for indirect jump
3552 // Fixme: Not triggering the use of both hi and low
3553 // This will generate an error message
3554 return std::make_pair(0U, nullptr);
3555 }
3556 }
3557
3558 std::pair<unsigned, const TargetRegisterClass *> R;
3559 R = parseRegForInlineAsmConstraint(Constraint, VT);
3560
3561 if (R.second)
3562 return R;
3563
3564 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3565 }
3566
3567 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3568 /// vector. If it is invalid, don't add anything to Ops.
LowerAsmOperandForConstraint(SDValue Op,std::string & Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const3569 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3570 std::string &Constraint,
3571 std::vector<SDValue>&Ops,
3572 SelectionDAG &DAG) const {
3573 SDLoc DL(Op);
3574 SDValue Result;
3575
3576 // Only support length 1 constraints for now.
3577 if (Constraint.length() > 1) return;
3578
3579 char ConstraintLetter = Constraint[0];
3580 switch (ConstraintLetter) {
3581 default: break; // This will fall through to the generic implementation
3582 case 'I': // Signed 16 bit constant
3583 // If this fails, the parent routine will give an error
3584 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3585 EVT Type = Op.getValueType();
3586 int64_t Val = C->getSExtValue();
3587 if (isInt<16>(Val)) {
3588 Result = DAG.getTargetConstant(Val, DL, Type);
3589 break;
3590 }
3591 }
3592 return;
3593 case 'J': // integer zero
3594 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3595 EVT Type = Op.getValueType();
3596 int64_t Val = C->getZExtValue();
3597 if (Val == 0) {
3598 Result = DAG.getTargetConstant(0, DL, Type);
3599 break;
3600 }
3601 }
3602 return;
3603 case 'K': // unsigned 16 bit immediate
3604 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3605 EVT Type = Op.getValueType();
3606 uint64_t Val = (uint64_t)C->getZExtValue();
3607 if (isUInt<16>(Val)) {
3608 Result = DAG.getTargetConstant(Val, DL, Type);
3609 break;
3610 }
3611 }
3612 return;
3613 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3614 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3615 EVT Type = Op.getValueType();
3616 int64_t Val = C->getSExtValue();
3617 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3618 Result = DAG.getTargetConstant(Val, DL, Type);
3619 break;
3620 }
3621 }
3622 return;
3623 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3624 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3625 EVT Type = Op.getValueType();
3626 int64_t Val = C->getSExtValue();
3627 if ((Val >= -65535) && (Val <= -1)) {
3628 Result = DAG.getTargetConstant(Val, DL, Type);
3629 break;
3630 }
3631 }
3632 return;
3633 case 'O': // signed 15 bit immediate
3634 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3635 EVT Type = Op.getValueType();
3636 int64_t Val = C->getSExtValue();
3637 if ((isInt<15>(Val))) {
3638 Result = DAG.getTargetConstant(Val, DL, Type);
3639 break;
3640 }
3641 }
3642 return;
3643 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3644 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3645 EVT Type = Op.getValueType();
3646 int64_t Val = C->getSExtValue();
3647 if ((Val <= 65535) && (Val >= 1)) {
3648 Result = DAG.getTargetConstant(Val, DL, Type);
3649 break;
3650 }
3651 }
3652 return;
3653 }
3654
3655 if (Result.getNode()) {
3656 Ops.push_back(Result);
3657 return;
3658 }
3659
3660 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3661 }
3662
isLegalAddressingMode(const DataLayout & DL,const AddrMode & AM,Type * Ty,unsigned AS) const3663 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3664 const AddrMode &AM, Type *Ty,
3665 unsigned AS) const {
3666 // No global is ever allowed as a base.
3667 if (AM.BaseGV)
3668 return false;
3669
3670 switch (AM.Scale) {
3671 case 0: // "r+i" or just "i", depending on HasBaseReg.
3672 break;
3673 case 1:
3674 if (!AM.HasBaseReg) // allow "r+i".
3675 break;
3676 return false; // disallow "r+r" or "r+r+i".
3677 default:
3678 return false;
3679 }
3680
3681 return true;
3682 }
3683
3684 bool
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const3685 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3686 // The Mips target isn't yet aware of offsets.
3687 return false;
3688 }
3689
getOptimalMemOpType(uint64_t Size,unsigned DstAlign,unsigned SrcAlign,bool IsMemset,bool ZeroMemset,bool MemcpyStrSrc,MachineFunction & MF) const3690 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3691 unsigned SrcAlign,
3692 bool IsMemset, bool ZeroMemset,
3693 bool MemcpyStrSrc,
3694 MachineFunction &MF) const {
3695 if (Subtarget.hasMips64())
3696 return MVT::i64;
3697
3698 return MVT::i32;
3699 }
3700
isFPImmLegal(const APFloat & Imm,EVT VT) const3701 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3702 if (VT != MVT::f32 && VT != MVT::f64)
3703 return false;
3704 if (Imm.isNegZero())
3705 return false;
3706 return Imm.isZero();
3707 }
3708
getJumpTableEncoding() const3709 unsigned MipsTargetLowering::getJumpTableEncoding() const {
3710 if (ABI.IsN64())
3711 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3712
3713 return TargetLowering::getJumpTableEncoding();
3714 }
3715
useSoftFloat() const3716 bool MipsTargetLowering::useSoftFloat() const {
3717 return Subtarget.useSoftFloat();
3718 }
3719
copyByValRegs(SDValue Chain,const SDLoc & DL,std::vector<SDValue> & OutChains,SelectionDAG & DAG,const ISD::ArgFlagsTy & Flags,SmallVectorImpl<SDValue> & InVals,const Argument * FuncArg,unsigned FirstReg,unsigned LastReg,const CCValAssign & VA,MipsCCState & State) const3720 void MipsTargetLowering::copyByValRegs(
3721 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
3722 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
3723 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
3724 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
3725 MipsCCState &State) const {
3726 MachineFunction &MF = DAG.getMachineFunction();
3727 MachineFrameInfo *MFI = MF.getFrameInfo();
3728 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
3729 unsigned NumRegs = LastReg - FirstReg;
3730 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
3731 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3732 int FrameObjOffset;
3733 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
3734
3735 if (RegAreaSize)
3736 FrameObjOffset =
3737 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3738 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
3739 else
3740 FrameObjOffset = VA.getLocMemOffset();
3741
3742 // Create frame object.
3743 EVT PtrTy = getPointerTy(DAG.getDataLayout());
3744 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3745 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3746 InVals.push_back(FIN);
3747
3748 if (!NumRegs)
3749 return;
3750
3751 // Copy arg registers.
3752 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
3753 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3754
3755 for (unsigned I = 0; I < NumRegs; ++I) {
3756 unsigned ArgReg = ByValArgRegs[FirstReg + I];
3757 unsigned VReg = addLiveIn(MF, ArgReg, RC);
3758 unsigned Offset = I * GPRSizeInBytes;
3759 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3760 DAG.getConstant(Offset, DL, PtrTy));
3761 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3762 StorePtr, MachinePointerInfo(FuncArg, Offset),
3763 false, false, 0);
3764 OutChains.push_back(Store);
3765 }
3766 }
3767
3768 // Copy byVal arg to registers and stack.
passByValArg(SDValue Chain,const SDLoc & DL,std::deque<std::pair<unsigned,SDValue>> & RegsToPass,SmallVectorImpl<SDValue> & MemOpChains,SDValue StackPtr,MachineFrameInfo * MFI,SelectionDAG & DAG,SDValue Arg,unsigned FirstReg,unsigned LastReg,const ISD::ArgFlagsTy & Flags,bool isLittle,const CCValAssign & VA) const3769 void MipsTargetLowering::passByValArg(
3770 SDValue Chain, const SDLoc &DL,
3771 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3772 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3773 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
3774 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
3775 const CCValAssign &VA) const {
3776 unsigned ByValSizeInBytes = Flags.getByValSize();
3777 unsigned OffsetInBytes = 0; // From beginning of struct
3778 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3779 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
3780 EVT PtrTy = getPointerTy(DAG.getDataLayout()),
3781 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3782 unsigned NumRegs = LastReg - FirstReg;
3783
3784 if (NumRegs) {
3785 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
3786 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
3787 unsigned I = 0;
3788
3789 // Copy words to registers.
3790 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
3791 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3792 DAG.getConstant(OffsetInBytes, DL, PtrTy));
3793 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3794 MachinePointerInfo(), false, false, false,
3795 Alignment);
3796 MemOpChains.push_back(LoadVal.getValue(1));
3797 unsigned ArgReg = ArgRegs[FirstReg + I];
3798 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3799 }
3800
3801 // Return if the struct has been fully copied.
3802 if (ByValSizeInBytes == OffsetInBytes)
3803 return;
3804
3805 // Copy the remainder of the byval argument with sub-word loads and shifts.
3806 if (LeftoverBytes) {
3807 SDValue Val;
3808
3809 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
3810 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
3811 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
3812
3813 if (RemainingSizeInBytes < LoadSizeInBytes)
3814 continue;
3815
3816 // Load subword.
3817 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3818 DAG.getConstant(OffsetInBytes, DL,
3819 PtrTy));
3820 SDValue LoadVal = DAG.getExtLoad(
3821 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
3822 MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false,
3823 Alignment);
3824 MemOpChains.push_back(LoadVal.getValue(1));
3825
3826 // Shift the loaded value.
3827 unsigned Shamt;
3828
3829 if (isLittle)
3830 Shamt = TotalBytesLoaded * 8;
3831 else
3832 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
3833
3834 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3835 DAG.getConstant(Shamt, DL, MVT::i32));
3836
3837 if (Val.getNode())
3838 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3839 else
3840 Val = Shift;
3841
3842 OffsetInBytes += LoadSizeInBytes;
3843 TotalBytesLoaded += LoadSizeInBytes;
3844 Alignment = std::min(Alignment, LoadSizeInBytes);
3845 }
3846
3847 unsigned ArgReg = ArgRegs[FirstReg + I];
3848 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3849 return;
3850 }
3851 }
3852
3853 // Copy remainder of byval arg to it with memcpy.
3854 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
3855 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3856 DAG.getConstant(OffsetInBytes, DL, PtrTy));
3857 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3858 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
3859 Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
3860 DAG.getConstant(MemCpySize, DL, PtrTy),
3861 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
3862 /*isTailCall=*/false,
3863 MachinePointerInfo(), MachinePointerInfo());
3864 MemOpChains.push_back(Chain);
3865 }
3866
writeVarArgRegs(std::vector<SDValue> & OutChains,SDValue Chain,const SDLoc & DL,SelectionDAG & DAG,CCState & State) const3867 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3868 SDValue Chain, const SDLoc &DL,
3869 SelectionDAG &DAG,
3870 CCState &State) const {
3871 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
3872 unsigned Idx = State.getFirstUnallocated(ArgRegs);
3873 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3874 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3875 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3876 MachineFunction &MF = DAG.getMachineFunction();
3877 MachineFrameInfo *MFI = MF.getFrameInfo();
3878 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3879
3880 // Offset of the first variable argument from stack pointer.
3881 int VaArgOffset;
3882
3883 if (ArgRegs.size() == Idx)
3884 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes);
3885 else {
3886 VaArgOffset =
3887 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3888 (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
3889 }
3890
3891 // Record the frame index of the first variable argument
3892 // which is a value necessary to VASTART.
3893 int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3894 MipsFI->setVarArgsFrameIndex(FI);
3895
3896 // Copy the integer registers that have not been used for argument passing
3897 // to the argument register save area. For O32, the save area is allocated
3898 // in the caller's stack frame, while for N32/64, it is allocated in the
3899 // callee's stack frame.
3900 for (unsigned I = Idx; I < ArgRegs.size();
3901 ++I, VaArgOffset += RegSizeInBytes) {
3902 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3903 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3904 FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3905 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3906 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3907 MachinePointerInfo(), false, false, 0);
3908 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
3909 (Value *)nullptr);
3910 OutChains.push_back(Store);
3911 }
3912 }
3913
HandleByVal(CCState * State,unsigned & Size,unsigned Align) const3914 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
3915 unsigned Align) const {
3916 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
3917
3918 assert(Size && "Byval argument's size shouldn't be 0.");
3919
3920 Align = std::min(Align, TFL->getStackAlignment());
3921
3922 unsigned FirstReg = 0;
3923 unsigned NumRegs = 0;
3924
3925 if (State->getCallingConv() != CallingConv::Fast) {
3926 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3927 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
3928 // FIXME: The O32 case actually describes no shadow registers.
3929 const MCPhysReg *ShadowRegs =
3930 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
3931
3932 // We used to check the size as well but we can't do that anymore since
3933 // CCState::HandleByVal() rounds up the size after calling this function.
3934 assert(!(Align % RegSizeInBytes) &&
3935 "Byval argument's alignment should be a multiple of"
3936 "RegSizeInBytes.");
3937
3938 FirstReg = State->getFirstUnallocated(IntArgRegs);
3939
3940 // If Align > RegSizeInBytes, the first arg register must be even.
3941 // FIXME: This condition happens to do the right thing but it's not the
3942 // right way to test it. We want to check that the stack frame offset
3943 // of the register is aligned.
3944 if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
3945 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
3946 ++FirstReg;
3947 }
3948
3949 // Mark the registers allocated.
3950 Size = alignTo(Size, RegSizeInBytes);
3951 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
3952 Size -= RegSizeInBytes, ++I, ++NumRegs)
3953 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3954 }
3955
3956 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
3957 }
3958
emitPseudoSELECT(MachineInstr & MI,MachineBasicBlock * BB,bool isFPCmp,unsigned Opc) const3959 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
3960 MachineBasicBlock *BB,
3961 bool isFPCmp,
3962 unsigned Opc) const {
3963 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
3964 "Subtarget already supports SELECT nodes with the use of"
3965 "conditional-move instructions.");
3966
3967 const TargetInstrInfo *TII =
3968 Subtarget.getInstrInfo();
3969 DebugLoc DL = MI.getDebugLoc();
3970
3971 // To "insert" a SELECT instruction, we actually have to insert the
3972 // diamond control-flow pattern. The incoming instruction knows the
3973 // destination vreg to set, the condition code register to branch on, the
3974 // true/false values to select between, and a branch opcode to use.
3975 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3976 MachineFunction::iterator It = ++BB->getIterator();
3977
3978 // thisMBB:
3979 // ...
3980 // TrueVal = ...
3981 // setcc r1, r2, r3
3982 // bNE r1, r0, copy1MBB
3983 // fallthrough --> copy0MBB
3984 MachineBasicBlock *thisMBB = BB;
3985 MachineFunction *F = BB->getParent();
3986 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3987 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3988 F->insert(It, copy0MBB);
3989 F->insert(It, sinkMBB);
3990
3991 // Transfer the remainder of BB and its successor edges to sinkMBB.
3992 sinkMBB->splice(sinkMBB->begin(), BB,
3993 std::next(MachineBasicBlock::iterator(MI)), BB->end());
3994 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3995
3996 // Next, add the true and fallthrough blocks as its successors.
3997 BB->addSuccessor(copy0MBB);
3998 BB->addSuccessor(sinkMBB);
3999
4000 if (isFPCmp) {
4001 // bc1[tf] cc, sinkMBB
4002 BuildMI(BB, DL, TII->get(Opc))
4003 .addReg(MI.getOperand(1).getReg())
4004 .addMBB(sinkMBB);
4005 } else {
4006 // bne rs, $0, sinkMBB
4007 BuildMI(BB, DL, TII->get(Opc))
4008 .addReg(MI.getOperand(1).getReg())
4009 .addReg(Mips::ZERO)
4010 .addMBB(sinkMBB);
4011 }
4012
4013 // copy0MBB:
4014 // %FalseValue = ...
4015 // # fallthrough to sinkMBB
4016 BB = copy0MBB;
4017
4018 // Update machine-CFG edges
4019 BB->addSuccessor(sinkMBB);
4020
4021 // sinkMBB:
4022 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4023 // ...
4024 BB = sinkMBB;
4025
4026 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4027 .addReg(MI.getOperand(2).getReg())
4028 .addMBB(thisMBB)
4029 .addReg(MI.getOperand(3).getReg())
4030 .addMBB(copy0MBB);
4031
4032 MI.eraseFromParent(); // The pseudo instruction is gone now.
4033
4034 return BB;
4035 }
4036
4037 // FIXME? Maybe this could be a TableGen attribute on some registers and
4038 // this table could be generated automatically from RegInfo.
getRegisterByName(const char * RegName,EVT VT,SelectionDAG & DAG) const4039 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4040 SelectionDAG &DAG) const {
4041 // Named registers is expected to be fairly rare. For now, just support $28
4042 // since the linux kernel uses it.
4043 if (Subtarget.isGP64bit()) {
4044 unsigned Reg = StringSwitch<unsigned>(RegName)
4045 .Case("$28", Mips::GP_64)
4046 .Default(0);
4047 if (Reg)
4048 return Reg;
4049 } else {
4050 unsigned Reg = StringSwitch<unsigned>(RegName)
4051 .Case("$28", Mips::GP)
4052 .Default(0);
4053 if (Reg)
4054 return Reg;
4055 }
4056 report_fatal_error("Invalid register name global variable");
4057 }
4058