| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/cconv/ |
| D | callee-saved-fpxx1.ll | 21 ; O32-FPXX-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
22 ; O32-FPXX-DAG: ldc1 [[F20]], [[OFF20]]($sp)
|
| D | callee-saved-float.ll | 57 ; O32-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
63 ; O32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
76 ; N32-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
82 ; N32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
|
| D | callee-saved-fpxx.ll | 46 ; O32-FPXX-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
52 ; O32-FPXX-DAG: ldc1 [[F20]], [[OFF20]]($sp)
|
| /external/llvm/test/CodeGen/Mips/cconv/ |
| D | callee-saved-fpxx1.ll | 21 ; O32-FPXX-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
22 ; O32-FPXX-DAG: ldc1 [[F20]], [[OFF20]]($sp)
|
| D | callee-saved-float.ll | 57 ; O32-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
63 ; O32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
76 ; N32-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
82 ; N32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
|
| D | callee-saved-fpxx.ll | 46 ; O32-FPXX-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
52 ; O32-FPXX-DAG: ldc1 [[F20]], [[OFF20]]($sp)
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaCallingConv.td | 31 [F16, F17, F18, F19, F20, F21]>>,
33 CCIfType<[f32, f64], CCAssignToRegWithShadow<[F16, F17, F18, F19, F20, F21],
|
| D | AlphaRegisterInfo.td | 92 def F20 : FPR<20, "$f20">, DwarfRegNum<[53]>;
128 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
|
| /external/mdnsresponder/ |
| D | mDNSResponder.sln | 46 …-00A0C91BC942}") = "Java", "mDNSWindows\Java\Java.vcproj", "{9CE2568A-3170-41C6-9F20-A0188A9EC114}"
53 {9CE2568A-3170-41C6-9F20-A0188A9EC114} = {9CE2568A-3170-41C6-9F20-A0188A9EC114}
252 {9CE2568A-3170-41C6-9F20-A0188A9EC114}.Debug|Any CPU.ActiveCfg = Debug|x64
253 {9CE2568A-3170-41C6-9F20-A0188A9EC114}.Debug|Mixed Platforms.ActiveCfg = Debug|x64
254 {9CE2568A-3170-41C6-9F20-A0188A9EC114}.Debug|Mixed Platforms.Build.0 = Debug|x64
255 {9CE2568A-3170-41C6-9F20-A0188A9EC114}.Debug|Win32.ActiveCfg = Debug|Win32
256 {9CE2568A-3170-41C6-9F20-A0188A9EC114}.Debug|Win32.Build.0 = Debug|Win32
257 {9CE2568A-3170-41C6-9F20-A0188A9EC114}.Debug|x64.ActiveCfg = Debug|x64
258 {9CE2568A-3170-41C6-9F20-A0188A9EC114}.Debug|x64.Build.0 = Debug|x64
259 {9CE2568A-3170-41C6-9F20-A0188A9EC114}.Release|Any CPU.ActiveCfg = Release|x64
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 106 def F20 : Rf<20, "F20">, DwarfRegNum<[52]>;
130 def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>;
|
| D | FPMover.cpp | 64 SP::F16, SP::F18, SP::F20, SP::F22, SP::F24, SP::F26, SP::F28, SP::F30 in getDoubleRegPair()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 162 def F20 : FPR<20, "F20">, DwarfRegNum<[52]>;
187 def D10 : AFPR<20, "F20", [F20, F21]>;
215 def D20_64 : AFPR64<20, "F20", [F20]>;
|
| D | MipsRegisterInfo.cpp | 104 case Mips::S4: case Mips::S4_64: case Mips::F20: case Mips::D20_64: in getRegisterNumbering()
152 Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, in getCalleeSavedRegs()
|
| /external/libopus/src/ |
| D | opus_decoder.c | 247 int F2_5, F5, F10, F20; in opus_decode_frame() local
255 F20 = st->Fs/50; in opus_decode_frame()
256 F10 = F20>>1; in opus_decode_frame()
295 if (audiosize > F20) in opus_decode_frame()
298 int ret = opus_decode_frame(st, NULL, 0, pcm, IMIN(audiosize, F20), 0); in opus_decode_frame()
309 } else if (audiosize < F20) in opus_decode_frame()
513 int celt_frame_size = IMIN(F20, frame_size); in opus_decode_frame()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCFrameLowering.h | 145 {PPC::F20, -96}, in getCalleeSavedSpillSlots()
222 {PPC::F20, -96}, in getCalleeSavedSpillSlots()
|
| D | PPCRegisterInfo.cpp | 113 PPC::F18, PPC::F19, PPC::F20, PPC::F21, in getCalleeSavedRegs()
139 PPC::F18, PPC::F19, PPC::F20, PPC::F21, in getCalleeSavedRegs()
167 PPC::F18, PPC::F19, PPC::F20, PPC::F21, in getCalleeSavedRegs()
193 PPC::F18, PPC::F19, PPC::F20, PPC::F21, in getCalleeSavedRegs()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 182 def F20 : Rf<20, "F20">, DwarfRegNum<[52]>;
206 def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>;
272 def Q5 : Rq<20, "F20", [D10, D11]>;
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 182 def F20 : Rf<20, "F20">, DwarfRegNum<[52]>;
206 def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>;
272 def Q5 : Rq<20, "F20", [D10, D11]>;
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 225 F19, F20, F21, F22, F23, F24, F25, F26,
234 F19, F20, F21, F22, F23, F24, F25, F26,
243 F19, F20, F21, F22, F23, F24, F25, F26,
252 F19, F20, F21, F22, F23, F24, F25, F26,
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCBaseInfo.h | 51 case R20: case X20: case F20: case V20: case CR5LT: return 20; in getPPCRegisterNumbering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 280 F19, F20, F21, F22, F23, F24, F25, F26,
292 F19, F20, F21, F22, F23, F24, F25, F26,
306 F19, F20, F21, F22, F23, F24, F25, F26,
315 F19, F20, F21, F22, F23, F24, F25, F26,
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 87 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
129 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
149 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/MCTargetDesc/ |
| D | MipsBaseInfo.h | 77 case Mips::S4: case Mips::S4_64: case Mips::F20: case Mips::D20_64: in getMipsRegisterNumbering()
|
| /external/libxkbcommon/xkbcommon/test/data/keycodes/ |
| D | evdev-xkbcommon | 191 <F20> = 190;
376 alias <FK20> = <F20>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 87 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
140 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
160 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
|