1; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s 2; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s 3; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV %s 4; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV %s 5 6; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s 7; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s 8; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV,O32-FPXX-INV %s 9; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV,O32-FPXX-INV %s 10 11define void @fpu_clobber() nounwind { 12entry: 13 call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f13},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() 14 ret void 15} 16 17; O32-FPXX-LABEL: fpu_clobber: 18; O32-FPXX-INV-NOT: sdc1 $f0, 19; O32-FPXX-INV-NOT: sdc1 $f1, 20; O32-FPXX-INV-NOT: sdc1 $f2, 21; O32-FPXX-INV-NOT: sdc1 $f3, 22; O32-FPXX-INV-NOT: sdc1 $f4, 23; O32-FPXX-INV-NOT: sdc1 $f5, 24; O32-FPXX-INV-NOT: sdc1 $f6, 25; O32-FPXX-INV-NOT: sdc1 $f7, 26; O32-FPXX-INV-NOT: sdc1 $f8, 27; O32-FPXX-INV-NOT: sdc1 $f9, 28; O32-FPXX-INV-NOT: sdc1 $f10, 29; O32-FPXX-INV-NOT: sdc1 $f11, 30; O32-FPXX-INV-NOT: sdc1 $f12, 31; O32-FPXX-INV-NOT: sdc1 $f13, 32; O32-FPXX-INV-NOT: sdc1 $f14, 33; O32-FPXX-INV-NOT: sdc1 $f15, 34; O32-FPXX-INV-NOT: sdc1 $f16, 35; O32-FPXX-INV-NOT: sdc1 $f17, 36; O32-FPXX-INV-NOT: sdc1 $f18, 37; O32-FPXX-INV-NOT: sdc1 $f19, 38; O32-FPXX-INV-NOT: sdc1 $f21, 39; O32-FPXX-INV-NOT: sdc1 $f23, 40; O32-FPXX-INV-NOT: sdc1 $f25, 41; O32-FPXX-INV-NOT: sdc1 $f27, 42; O32-FPXX-INV-NOT: sdc1 $f29, 43; O32-FPXX-INV-NOT: sdc1 $f31, 44 45; O32-FPXX: addiu $sp, $sp, -48 46; O32-FPXX-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp) 47; O32-FPXX-DAG: sdc1 [[F22:\$f22]], [[OFF22:[0-9]+]]($sp) 48; O32-FPXX-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp) 49; O32-FPXX-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp) 50; O32-FPXX-DAG: sdc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp) 51; O32-FPXX-DAG: sdc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp) 52; O32-FPXX-DAG: ldc1 [[F20]], [[OFF20]]($sp) 53; O32-FPXX-DAG: ldc1 [[F22]], [[OFF22]]($sp) 54; O32-FPXX-DAG: ldc1 [[F24]], [[OFF24]]($sp) 55; O32-FPXX-DAG: ldc1 [[F26]], [[OFF26]]($sp) 56; O32-FPXX-DAG: ldc1 [[F28]], [[OFF28]]($sp) 57; O32-FPXX-DAG: ldc1 [[F30]], [[OFF30]]($sp) 58; O32-FPXX: addiu $sp, $sp, 48 59