| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 1489 X86_INTRINSIC_DATA(avx512_mask_vfmadd_pd_128, FMA_OP_MASK, X86ISD::FMADD, 0),
1490 X86_INTRINSIC_DATA(avx512_mask_vfmadd_pd_256, FMA_OP_MASK, X86ISD::FMADD, 0),
1491 X86_INTRINSIC_DATA(avx512_mask_vfmadd_pd_512, FMA_OP_MASK, X86ISD::FMADD,
1493 X86_INTRINSIC_DATA(avx512_mask_vfmadd_ps_128, FMA_OP_MASK, X86ISD::FMADD, 0),
1494 X86_INTRINSIC_DATA(avx512_mask_vfmadd_ps_256, FMA_OP_MASK, X86ISD::FMADD, 0),
1495 X86_INTRINSIC_DATA(avx512_mask_vfmadd_ps_512, FMA_OP_MASK, X86ISD::FMADD,
1629 X86_INTRINSIC_DATA(avx512_mask3_vfmadd_pd_128, FMA_OP_MASK3, X86ISD::FMADD, 0),
1630 X86_INTRINSIC_DATA(avx512_mask3_vfmadd_pd_256, FMA_OP_MASK3, X86ISD::FMADD, 0),
1631 X86_INTRINSIC_DATA(avx512_mask3_vfmadd_pd_512, FMA_OP_MASK3, X86ISD::FMADD,
1633 X86_INTRINSIC_DATA(avx512_mask3_vfmadd_ps_128, FMA_OP_MASK3, X86ISD::FMADD, 0),
[all …]
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| D | X86ISelLowering.h | 474 FMADD, enumerator
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| D | X86InstrFragmentsSIMD.td | 469 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | README_ALTIVEC.txt | 25 Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
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| D | PPCInstrInfo.td | 1225 def FMADD : AForm_1<63, 29,
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| /external/v8/src/ppc/ |
| D | disasm-ppc.cc | 991 case FMADD: { in DecodeExt4()
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| D | constants-ppc.h | 1846 V(fmadd, FMADD, 0xFC00003A) \
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| D | assembler-ppc.cc | 1940 emit(EXT4 | FMADD | frt.code() * B21 | fra.code() * B16 | frb.code() * B11 | in fmadd()
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| D | simulator-ppc.cc | 3350 case FMADD: { in ExecuteGeneric()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | README_ALTIVEC.txt | 25 Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
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| D | P9InstrResources.td | 416 (instregex "FMADD(S)?$"),
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| /external/llvm/lib/Target/PowerPC/ |
| D | README_ALTIVEC.txt | 25 Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
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| /external/v8/src/mips/ |
| D | constants-mips.h | 919 FMADD = ((4U << 22) + 27), enumerator
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| D | disasm-mips.cc | 2508 case FMADD: in DecodeTypeMsa3RF()
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| D | simulator-mips.cc | 5418 case FMADD: in Msa3RFInstrHelper()
5701 if (opcode == FMADD || opcode == FMSUB) { in DecodeTypeMsa3RF()
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| D | assembler-mips.cc | 3555 V(fmadd, FMADD) \
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 953 FMADD = ((4U << 22) + 27), enumerator
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| D | disasm-mips64.cc | 2822 case FMADD: in DecodeTypeMsa3RF()
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| D | simulator-mips64.cc | 5642 case FMADD: in Msa3RFInstrHelper()
5925 if (opcode == FMADD || opcode == FMSUB) { in DecodeTypeMsa3RF()
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| /external/v8/src/arm64/ |
| D | disasm-arm64.cc | 1084 FORMAT(FMADD, "fmadd"); in VisitFPDataProcessing3Source()
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| /external/vixl/src/aarch64/ |
| D | disasm-aarch64.cc | 1750 FORMAT(FMADD, "fmadd"); in VisitFPDataProcessing3Source()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedThunderX2T99.td | 1182 (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
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| /external/capstone/arch/PowerPC/ |
| D | PPCGenAsmWriter.inc | 522 18697U, // FMADD
1795 40U, // FMADD
4016 // FMADD, FMADDS, FMADDSo, FMADDo, FMSUB, FMSUBS, FMSUBSo, FMSUBo, FNMADD...
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| D | PPCGenDisassemblerTables.inc | 2223 /* 9328 */ MCD_OPC_Decode, 246, 3, 112, // Opcode: FMADD
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2013 ### FMADD ### subsection
|