| /external/apache-commons-bcel/src/main/java/org/apache/bcel/generic/ |
| D | FNEG.java | 26 public class FNEG extends ArithmeticInstruction { class
28 public FNEG() { in FNEG() method in FNEG
29 super(org.apache.bcel.Const.FNEG); in FNEG()
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| D | InstructionConstants.java | 111 ArithmeticInstruction FNEG = new FNEG(); field
246 INSTRUCTIONS[Const.FNEG] = FNEG; in Clinit()
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| D | InstructionConst.java | 110 public static final ArithmeticInstruction FNEG = new FNEG(); field in InstructionConst
241 INSTRUCTIONS[Const.FNEG] = FNEG;
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| D | ArithmeticInstruction.java | 62 case Const.FNEG: in getType()
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| D | Visitor.java | 492 void visitFNEG( FNEG obj ); in visitFNEG()
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| D | EmptyVisitor.java | 788 public void visitFNEG( final FNEG obj ) { in visitFNEG()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 467 setOperationAction(ISD::FNEG, VT, Expand); in AMDGPUTargetLowering()
533 setTargetDAGCombine(ISD::FNEG); in AMDGPUTargetLowering()
1505 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq); in LowerDIVREM24()
2379 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R); in LowerINT_TO_FP32()
3353 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) { in foldFreeOpFromSelect()
3359 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) { in foldFreeOpFromSelect()
3366 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) { in foldFreeOpFromSelect()
3378 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc)) in foldFreeOpFromSelect()
3385 if (LHS.getOpcode() == ISD::FNEG) in foldFreeOpFromSelect()
3386 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in foldFreeOpFromSelect()
[all …]
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| D | AMDGPUISelDAGToDAG.cpp | 1837 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3ModsImpl()
1868 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG) in SelectVOP3NoMods()
1944 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
1955 if (Lo.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
1960 if (Hi.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 172 case ISD::FNEG: in LegalizeOp()
221 else if (Node->getOpcode() == ISD::FNEG) in LegalizeOp()
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| D | LegalizeFloatTypes.cpp | 81 case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break; in SoftenFloatResult()
864 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; in ExpandFloatResult()
905 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), in ExpandFloatRes_FABS()
1055 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo); in ExpandFloatRes_FNEG()
1056 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi); in ExpandFloatRes_FNEG()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 1010 if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps()) { in SelectBitOp()
1016 if (Opc != ISD::FABS && Opc != ISD::FNEG) { in SelectBitOp()
1053 if (Opc != ISD::FABS && Opc != ISD::FNEG) { in SelectBitOp()
1080 case ISD::FNEG: in SelectBitOp()
1124 if (Opc != ISD::FABS && Opc != ISD::FNEG) in SelectBitOp()
1232 case ISD::FNEG: in Select()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 450 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
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| /external/llvm/test/CodeGen/X86/ |
| D | fnabs.ll | 4 ; FNABS(x) operation -> FNEG (FABS(x)).
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| D | vec_fneg.ll | 7 ; FNEG is defined as subtraction from -0.0.
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | fnabs.ll | 4 ; FNABS(x) operation -> FNEG (FABS(x)).
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| D | vec_fneg.ll | 7 ; FNEG is defined as subtraction from -0.0.
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 524 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 557 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 591 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
653 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
1419 case ISD::FNEG: return visitFNEG(N); in visit()
7367 FPOpcode = ISD::FNEG; in foldBitcastedFPLogic()
7466 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
7479 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
7498 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
7985 DAG.getNode(ISD::FNEG, SL, VT, N1)); in visitFSUBForFMACombine()
7993 DAG.getNode(ISD::FNEG, SL, VT, in visitFSUBForFMACombine()
7998 if (N0.getOpcode() == ISD::FNEG && in visitFSUBForFMACombine()
[all …]
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| D | LegalizeFloatTypes.cpp | 93 case ISD::FNEG: R = SoftenFloatRes_FNEG(N, ResNo); break; in SoftenFloatResult()
803 case ISD::FNEG: in CanSkipSoftenFloatOperand()
818 case ISD::FNEG: in CanSkipSoftenFloatOperand()
1033 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; in ExpandFloatResult()
1079 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), in ExpandFloatRes_FABS()
1263 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo); in ExpandFloatRes_FNEG()
1264 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi); in ExpandFloatRes_FNEG()
1879 case ISD::FNEG: in PromoteFloatResult()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 93 case ISD::FNEG: R = SoftenFloatRes_FNEG(N, ResNo); break; in SoftenFloatResult()
760 case ISD::FNEG: Res = SoftenFloatOp_FNEG(N); break; in SoftenFloatOperand()
809 case ISD::FNEG: in CanSkipSoftenFloatOperand()
1087 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; in ExpandFloatResult()
1133 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), in ExpandFloatRes_FABS()
1317 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo); in ExpandFloatRes_FNEG()
1318 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi); in ExpandFloatRes_FNEG()
1897 case ISD::FNEG: in PromoteFloatResult()
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| D | DAGCombiner.cpp | 682 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
753 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
1574 case ISD::FNEG: return visitFNEG(N); in visit()
9712 FPOpcode = ISD::FNEG; in foldBitcastedFPLogic()
9813 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
9826 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
9845 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
10376 DAG.getNode(ISD::FNEG, SL, VT, N1), Flags); in visitFSUBForFMACombine()
10383 DAG.getNode(ISD::FNEG, SL, VT, in visitFSUBForFMACombine()
10389 if (N0.getOpcode() == ISD::FNEG && isContractableFMUL(N0.getOperand(0)) && in visitFSUBForFMACombine()
[all …]
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| D | LegalizeVectorOps.cpp | 360 case ISD::FNEG: in LegalizeOp()
725 case ISD::FNEG: in Expand()
1082 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && in ExpandFSUB()
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| /external/apache-commons-bcel/src/main/java/org/apache/bcel/ |
| D | Constants.java | 752 short FNEG = 118; field
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| /external/jacoco/org.jacoco.core.test/src/org/jacoco/core/internal/flow/ |
| D | LabelFlowAnalyzerTest.java | 210 testInsn(FNEG, true); in testInsn()
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