| /external/u-boot/board/samsung/odroid/ |
| D | odroid.c | 119 clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1); in board_clock_init()
120 set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1); in board_clock_init()
203 set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); in board_clock_init()
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| D | setup.h | 14 #define FSEL(x) (((x) & 0x1) << 27) macro
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 31 FSEL, enumerator
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| D | README.txt | 911 ; This could generate FSEL with appropriate flags (FSEL is not IEEE-safe, and
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| D | PPCISelLowering.cpp | 428 case PPCISD::FSEL: return "PPCISD::FSEL"; in getTargetNodeName()
3600 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
3608 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
3620 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
3626 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
3632 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
3638 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
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| D | PPCInstrInfo.td | 83 def PPCfsel : SDNode<"PPCISD::FSEL",
1274 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
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| /external/llvm/lib/Target/PowerPC/ |
| D | README.txt | 606 ; This could generate FSEL with appropriate flags (FSEL is not IEEE-safe, and
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| D | PPCISelLowering.h | 33 FSEL, enumerator
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| D | PPCISelLowering.cpp | 1009 case PPCISD::FSEL: return "PPCISD::FSEL"; in getTargetNodeName()
6310 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6313 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6322 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6330 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6343 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6346 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6353 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
6359 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6365 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
[all …]
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| D | PPCInstrInfo.td | 120 def PPCfsel : SDNode<"PPCISD::FSEL",
2571 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | README.txt | 606 ; This could generate FSEL with appropriate flags (FSEL is not IEEE-safe, and
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| D | PPCISelLowering.h | 54 FSEL, enumerator
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| D | PPCISelLowering.cpp | 1253 case PPCISD::FSEL: return "PPCISD::FSEL"; in getTargetNodeName()
6877 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6880 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6890 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6899 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6913 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6916 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6923 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
6929 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6935 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
[all …]
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| D | P9InstrResources.td | 456 (instregex "FSEL(D|S)o$")
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| D | PPCInstrInfo.td | 161 def PPCfsel : SDNode<"PPCISD::FSEL",
2851 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
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| /external/v8/src/ppc/ |
| D | disasm-ppc.cc | 979 case FSEL: { in DecodeExt4()
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| D | constants-ppc.h | 1870 V(fsel, FSEL, 0xFC00002E) \
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| D | assembler-ppc.cc | 1884 emit(EXT4 | FSEL | frt.code() * B21 | fra.code() * B16 | frb.code() * B11 | in fsel()
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| D | simulator-ppc.cc | 3316 case FSEL: { in ExecuteGeneric()
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