Searched refs:FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK (Results 1 – 3 of 3) sorted by relevance
54 cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in serdes_get_first_lane()186 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in setup_serdes_volt()367 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in setup_serdes_volt()415 FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK, in fsl_serdes_init()
266 FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in board_eth_init()
270 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff macro