1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <netdev.h>
9 #include <fdt_support.h>
10 #include <fm_eth.h>
11 #include <fsl_mdio.h>
12 #include <fsl_dtsec.h>
13 #include <malloc.h>
14 #include <asm/arch/fsl_serdes.h>
15
16 #include "../common/qixis.h"
17 #include "../common/fman.h"
18 #include "ls1046aqds_qixis.h"
19
20 #define EMI_NONE 0xFF
21 #define EMI1_RGMII1 0
22 #define EMI1_RGMII2 1
23 #define EMI1_SLOT1 2
24 #define EMI1_SLOT2 3
25 #define EMI1_SLOT4 4
26
27 static int mdio_mux[NUM_FM_PORTS];
28
29 static const char * const mdio_names[] = {
30 "LS1046AQDS_MDIO_RGMII1",
31 "LS1046AQDS_MDIO_RGMII2",
32 "LS1046AQDS_MDIO_SLOT1",
33 "LS1046AQDS_MDIO_SLOT2",
34 "LS1046AQDS_MDIO_SLOT4",
35 "NULL",
36 };
37
38 /* Map SerDes 1 & 2 lanes to default slot. */
39 static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0};
40
ls1046aqds_mdio_name_for_muxval(u8 muxval)41 static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval)
42 {
43 return mdio_names[muxval];
44 }
45
mii_dev_for_muxval(u8 muxval)46 struct mii_dev *mii_dev_for_muxval(u8 muxval)
47 {
48 struct mii_dev *bus;
49 const char *name;
50
51 if (muxval > EMI1_SLOT4)
52 return NULL;
53
54 name = ls1046aqds_mdio_name_for_muxval(muxval);
55
56 if (!name) {
57 printf("No bus for muxval %x\n", muxval);
58 return NULL;
59 }
60
61 bus = miiphy_get_dev_by_name(name);
62
63 if (!bus) {
64 printf("No bus by name %s\n", name);
65 return NULL;
66 }
67
68 return bus;
69 }
70
71 struct ls1046aqds_mdio {
72 u8 muxval;
73 struct mii_dev *realbus;
74 };
75
ls1046aqds_mux_mdio(u8 muxval)76 static void ls1046aqds_mux_mdio(u8 muxval)
77 {
78 u8 brdcfg4;
79
80 if (muxval < 7) {
81 brdcfg4 = QIXIS_READ(brdcfg[4]);
82 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
83 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
84 QIXIS_WRITE(brdcfg[4], brdcfg4);
85 }
86 }
87
ls1046aqds_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)88 static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
89 int regnum)
90 {
91 struct ls1046aqds_mdio *priv = bus->priv;
92
93 ls1046aqds_mux_mdio(priv->muxval);
94
95 return priv->realbus->read(priv->realbus, addr, devad, regnum);
96 }
97
ls1046aqds_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)98 static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
99 int regnum, u16 value)
100 {
101 struct ls1046aqds_mdio *priv = bus->priv;
102
103 ls1046aqds_mux_mdio(priv->muxval);
104
105 return priv->realbus->write(priv->realbus, addr, devad,
106 regnum, value);
107 }
108
ls1046aqds_mdio_reset(struct mii_dev * bus)109 static int ls1046aqds_mdio_reset(struct mii_dev *bus)
110 {
111 struct ls1046aqds_mdio *priv = bus->priv;
112
113 return priv->realbus->reset(priv->realbus);
114 }
115
ls1046aqds_mdio_init(char * realbusname,u8 muxval)116 static int ls1046aqds_mdio_init(char *realbusname, u8 muxval)
117 {
118 struct ls1046aqds_mdio *pmdio;
119 struct mii_dev *bus = mdio_alloc();
120
121 if (!bus) {
122 printf("Failed to allocate ls1046aqds MDIO bus\n");
123 return -1;
124 }
125
126 pmdio = malloc(sizeof(*pmdio));
127 if (!pmdio) {
128 printf("Failed to allocate ls1046aqds private data\n");
129 free(bus);
130 return -1;
131 }
132
133 bus->read = ls1046aqds_mdio_read;
134 bus->write = ls1046aqds_mdio_write;
135 bus->reset = ls1046aqds_mdio_reset;
136 sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval));
137
138 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
139
140 if (!pmdio->realbus) {
141 printf("No bus with name %s\n", realbusname);
142 free(bus);
143 free(pmdio);
144 return -1;
145 }
146
147 pmdio->muxval = muxval;
148 bus->priv = pmdio;
149 return mdio_register(bus);
150 }
151
board_ft_fman_fixup_port(void * fdt,char * compat,phys_addr_t addr,enum fm_port port,int offset)152 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
153 enum fm_port port, int offset)
154 {
155 struct fixed_link f_link;
156
157 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
158 switch (port) {
159 case FM1_DTSEC9:
160 fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p1");
161 break;
162 case FM1_DTSEC10:
163 fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p2");
164 break;
165 case FM1_DTSEC5:
166 fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p3");
167 break;
168 case FM1_DTSEC6:
169 fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p4");
170 break;
171 case FM1_DTSEC2:
172 fdt_set_phy_handle(fdt, compat, addr, "sgmii_s4_p1");
173 break;
174 default:
175 break;
176 }
177 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
178 /* 2.5G SGMII interface */
179 f_link.phy_id = cpu_to_fdt32(port);
180 f_link.duplex = cpu_to_fdt32(1);
181 f_link.link_speed = cpu_to_fdt32(1000);
182 f_link.pause = 0;
183 f_link.asym_pause = 0;
184 /* no PHY for 2.5G SGMII on QDS */
185 fdt_delprop(fdt, offset, "phy-handle");
186 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
187 fdt_setprop_string(fdt, offset, "phy-connection-type",
188 "sgmii-2500");
189 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
190 switch (port) {
191 case FM1_DTSEC1:
192 fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p4");
193 break;
194 case FM1_DTSEC5:
195 fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p2");
196 break;
197 case FM1_DTSEC6:
198 fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p1");
199 break;
200 case FM1_DTSEC10:
201 fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p3");
202 break;
203 default:
204 break;
205 }
206 fdt_delprop(fdt, offset, "phy-connection-type");
207 fdt_setprop_string(fdt, offset, "phy-connection-type",
208 "qsgmii");
209 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
210 (port == FM1_10GEC1 || port == FM1_10GEC2)) {
211 /* XFI interface */
212 f_link.phy_id = cpu_to_fdt32(port);
213 f_link.duplex = cpu_to_fdt32(1);
214 f_link.link_speed = cpu_to_fdt32(10000);
215 f_link.pause = 0;
216 f_link.asym_pause = 0;
217 /* no PHY for XFI */
218 fdt_delprop(fdt, offset, "phy-handle");
219 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
220 fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
221 }
222 }
223
fdt_fixup_board_enet(void * fdt)224 void fdt_fixup_board_enet(void *fdt)
225 {
226 int i;
227
228 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
229 switch (fm_info_get_enet_if(i)) {
230 case PHY_INTERFACE_MODE_SGMII:
231 case PHY_INTERFACE_MODE_QSGMII:
232 switch (mdio_mux[i]) {
233 case EMI1_SLOT1:
234 fdt_status_okay_by_alias(fdt, "emi1_slot1");
235 break;
236 case EMI1_SLOT2:
237 fdt_status_okay_by_alias(fdt, "emi1_slot2");
238 break;
239 case EMI1_SLOT4:
240 fdt_status_okay_by_alias(fdt, "emi1_slot4");
241 break;
242 default:
243 break;
244 }
245 break;
246 default:
247 break;
248 }
249 }
250 }
251
board_eth_init(bd_t * bis)252 int board_eth_init(bd_t *bis)
253 {
254 #ifdef CONFIG_FMAN_ENET
255 int i, idx, lane, slot, interface;
256 struct memac_mdio_info dtsec_mdio_info;
257 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
258 u32 srds_s1, srds_s2;
259 u8 brdcfg12;
260
261 srds_s1 = in_be32(&gur->rcwsr[4]) &
262 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
263 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
264
265 srds_s2 = in_be32(&gur->rcwsr[4]) &
266 FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
267 srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
268
269 /* Initialize the mdio_mux array so we can recognize empty elements */
270 for (i = 0; i < NUM_FM_PORTS; i++)
271 mdio_mux[i] = EMI_NONE;
272
273 dtsec_mdio_info.regs =
274 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
275
276 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
277
278 /* Register the 1G MDIO bus */
279 fm_memac_mdio_init(bis, &dtsec_mdio_info);
280
281 /* Register the muxing front-ends to the MDIO buses */
282 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
283 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
284 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
285 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
286 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
287
288 /* Set the two on-board RGMII PHY address */
289 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
290 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
291
292 switch (srds_s1) {
293 case 0x3333:
294 /* SGMII on slot 1, MAC 9 */
295 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
296 case 0x1333:
297 case 0x2333:
298 /* SGMII on slot 1, MAC 10 */
299 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
300 case 0x1133:
301 case 0x2233:
302 /* SGMII on slot 1, MAC 5/6 */
303 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
304 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
305 break;
306 case 0x1040:
307 case 0x2040:
308 /* QSGMII on lane B, MAC 6/5/10/1 */
309 fm_info_set_phy_address(FM1_DTSEC6,
310 QSGMII_CARD_PORT1_PHY_ADDR_S2);
311 fm_info_set_phy_address(FM1_DTSEC5,
312 QSGMII_CARD_PORT2_PHY_ADDR_S2);
313 fm_info_set_phy_address(FM1_DTSEC10,
314 QSGMII_CARD_PORT3_PHY_ADDR_S2);
315 fm_info_set_phy_address(FM1_DTSEC1,
316 QSGMII_CARD_PORT4_PHY_ADDR_S2);
317 break;
318 case 0x3363:
319 /* SGMII on slot 1, MAC 9/10 */
320 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
321 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
322 case 0x1163:
323 case 0x2263:
324 case 0x2223:
325 /* SGMII on slot 1, MAC 6 */
326 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
327 break;
328 default:
329 printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n",
330 srds_s1);
331 break;
332 }
333
334 if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06)
335 /* SGMII on slot 4, MAC 2 */
336 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
337
338 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
339 idx = i - FM1_DTSEC1;
340 interface = fm_info_get_enet_if(i);
341 switch (interface) {
342 case PHY_INTERFACE_MODE_SGMII:
343 case PHY_INTERFACE_MODE_QSGMII:
344 if (interface == PHY_INTERFACE_MODE_SGMII) {
345 if (i == FM1_DTSEC5) {
346 /* route lane 2 to slot1 so to have
347 * one sgmii riser card supports
348 * MAC5 and MAC6.
349 */
350 brdcfg12 = QIXIS_READ(brdcfg[12]);
351 QIXIS_WRITE(brdcfg[12],
352 brdcfg12 | 0x80);
353 }
354 lane = serdes_get_first_lane(FSL_SRDS_1,
355 SGMII_FM1_DTSEC1 + idx);
356 } else {
357 /* clear the bit 7 to route lane B on slot2. */
358 brdcfg12 = QIXIS_READ(brdcfg[12]);
359 QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f);
360
361 lane = serdes_get_first_lane(FSL_SRDS_1,
362 QSGMII_FM1_A);
363 lane_to_slot[lane] = 2;
364 }
365
366 if (i == FM1_DTSEC2)
367 lane = 5;
368
369 if (lane < 0)
370 break;
371
372 slot = lane_to_slot[lane];
373 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
374 idx + 1, slot);
375 if (QIXIS_READ(present2) & (1 << (slot - 1)))
376 fm_disable_port(i);
377
378 switch (slot) {
379 case 1:
380 mdio_mux[i] = EMI1_SLOT1;
381 fm_info_set_mdio(i, mii_dev_for_muxval(
382 mdio_mux[i]));
383 break;
384 case 2:
385 mdio_mux[i] = EMI1_SLOT2;
386 fm_info_set_mdio(i, mii_dev_for_muxval(
387 mdio_mux[i]));
388 break;
389 case 4:
390 mdio_mux[i] = EMI1_SLOT4;
391 fm_info_set_mdio(i, mii_dev_for_muxval(
392 mdio_mux[i]));
393 break;
394 default:
395 break;
396 }
397 break;
398 case PHY_INTERFACE_MODE_RGMII:
399 case PHY_INTERFACE_MODE_RGMII_TXID:
400 if (i == FM1_DTSEC3)
401 mdio_mux[i] = EMI1_RGMII1;
402 else if (i == FM1_DTSEC4)
403 mdio_mux[i] = EMI1_RGMII2;
404 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
405 break;
406 default:
407 break;
408 }
409 }
410
411 cpu_eth_init(bis);
412 #endif /* CONFIG_FMAN_ENET */
413
414 return pci_eth_init(bis);
415 }
416