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Searched refs:FirstReg (Results 1 – 25 of 26) sorted by relevance

12

/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp223 unsigned FirstReg = 0; in CreateRegs() local
231 if (!FirstReg) FirstReg = R; in CreateRegs()
234 return FirstReg; in CreateRegs()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp373 unsigned FirstReg = 0; in CreateRegs() local
381 if (!FirstReg) FirstReg = R; in CreateRegs()
384 return FirstReg; in CreateRegs()
/external/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp382 unsigned FirstReg = 0; in CreateRegs() local
390 if (!FirstReg) FirstReg = R; in CreateRegs()
393 return FirstReg; in CreateRegs()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp494 unsigned FirstReg = 0; in ScanInstruction() local
501 if (FirstReg != 0) { in ScanInstruction()
503 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
506 FirstReg = Reg; in ScanInstruction()
510 DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp506 unsigned FirstReg = 0; in ScanInstruction() local
513 if (FirstReg != 0) { in ScanInstruction()
515 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
518 FirstReg = Reg; in ScanInstruction()
522 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
/external/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp487 unsigned FirstReg = 0; in ScanInstruction() local
494 if (FirstReg != 0) { in ScanInstruction()
496 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
499 FirstReg = Reg; in ScanInstruction()
503 DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp2096 unsigned &FirstReg, in CanFormLdStDWord() argument
2158 FirstReg = Op0->getOperand(0).getReg(); in CanFormLdStDWord()
2160 if (FirstReg == SecondReg) in CanFormLdStDWord()
2263 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
2271 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2278 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2284 .addReg(FirstReg, RegState::Define) in RescheduleOps()
2298 .addReg(FirstReg) in RescheduleOps()
2316 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2317 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp2057 unsigned &FirstReg, in CanFormLdStDWord() argument
2119 FirstReg = Op0->getOperand(0).getReg(); in CanFormLdStDWord()
2121 if (FirstReg == SecondReg) in CanFormLdStDWord()
2217 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
2225 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2232 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2238 .addReg(FirstReg, RegState::Define) in RescheduleOps()
2252 .addReg(FirstReg) in RescheduleOps()
2270 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2271 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
DARMBaseInstrInfo.cpp2072 unsigned FirstReg = MI->getOperand(RegListIdx).getReg(); in tryFoldSPUpdateIntoPushPop() local
2093 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded; in tryFoldSPUpdateIntoPushPop()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
797 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
798 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
800 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
802 unsigned OldFirstReg = FirstReg; in insertSelect()
803 FirstReg = MRI.createVirtualRegister(FirstRC); in insertSelect()
804 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) in insertSelect()
809 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1202 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList64Operands() local
1205 MCOperand::createReg(FirstReg + getVectorListStart() - AArch64::Q0)); in addVectorList64Operands()
1215 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList128Operands() local
1218 MCOperand::createReg(FirstReg + getVectorListStart() - AArch64::Q0)); in addVectorList128Operands()
2979 int64_t FirstReg = tryMatchVectorRegister(Kind, true); in parseVectorList() local
2980 if (FirstReg == -1) in parseVectorList()
2982 int64_t PrevReg = FirstReg; in parseVectorList()
3041 FirstReg, Count, NumElements, ElementKind, S, getLoc(), getContext())); in parseVectorList()
4616 int FirstReg = tryParseRegister(); in tryParseGPRSeqPair() local
4617 if (FirstReg == -1) { in tryParseGPRSeqPair()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp3291 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadImmReal() local
3314 if (loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, true, IDLoc, in expandLoadImmReal()
3326 TOut.emitRR(Mips::MTC1, FirstReg, ATReg, IDLoc, STI); in expandLoadImmReal()
3349 TOut.emitRRX(Mips::LWC1, FirstReg, ATReg, in expandLoadImmReal()
3363 if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, false, true, in expandLoadImmReal()
3368 if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, true, true, in expandLoadImmReal()
3372 if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, true, in expandLoadImmReal()
3405 TOut.emitRRI(Mips::LD, FirstReg, ATReg, 0, IDLoc, STI); in expandLoadImmReal()
3407 TOut.emitRRI(Mips::LW, FirstReg, ATReg, 0, IDLoc, STI); in expandLoadImmReal()
3408 TOut.emitRRI(Mips::LW, nextReg(FirstReg), ATReg, 4, IDLoc, STI); in expandLoadImmReal()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1233 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1234 Reg = FirstReg; in printVectorList()
1235 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1236 Reg = FirstReg; in printVectorList()
1237 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
1238 Reg = FirstReg; in printVectorList()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp3724 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs() argument
3729 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs()
3738 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); in copyByValRegs()
3756 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs()
3773 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg() argument
3782 unsigned NumRegs = LastReg - FirstReg; in passByValArg()
3797 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
3847 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
3922 unsigned FirstReg = 0; in HandleByVal() local
3938 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
[all …]
DMipsISelLowering.h468 const Argument *FuncArg, unsigned FirstReg,
477 unsigned FirstReg, unsigned LastReg,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.cpp4028 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs() argument
4033 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs()
4042 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); in copyByValRegs()
4065 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs()
4081 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg() argument
4090 unsigned NumRegs = LastReg - FirstReg; in passByValArg()
4104 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4153 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4228 unsigned FirstReg = 0; in HandleByVal() local
4244 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
[all …]
DMipsISelLowering.h576 const Argument *FuncArg, unsigned FirstReg,
585 unsigned FirstReg, unsigned LastReg,
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1307 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1308 Reg = FirstReg; in printVectorList()
1309 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1310 Reg = FirstReg; in printVectorList()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1495 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
1496 Inst.addOperand(MCOperand::createReg(FirstReg + getVectorListStart() - in addVectorListOperands()
3191 unsigned FirstReg; in tryParseVectorList() local
3192 auto ParseRes = ParseVector(FirstReg, Kind, getLoc(), ExpectMatch); in tryParseVectorList()
3202 int64_t PrevReg = FirstReg; in tryParseVectorList()
3272 FirstReg, Count, NumElements, ElementWidth, VectorKind, S, getLoc(), in tryParseVectorList()
5405 unsigned FirstReg; in tryParseGPRSeqPair() local
5406 OperandMatchResultTy Res = tryParseScalarRegister(FirstReg); in tryParseGPRSeqPair()
5415 bool isXReg = XRegClass.contains(FirstReg), in tryParseGPRSeqPair()
5416 isWReg = WRegClass.contains(FirstReg); in tryParseGPRSeqPair()
[all …]
/external/capstone/arch/AArch64/
DAArch64InstPrinter.c1104 unsigned NumRegs = 1, FirstReg, i; in printVectorList() local
1121 if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_dsub0))) in printVectorList()
1122 Reg = FirstReg; in printVectorList()
1123 else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_qsub0))) in printVectorList()
1124 Reg = FirstReg; in printVectorList()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp843 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
849 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
850 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
852 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
854 unsigned OldFirstReg = FirstReg; in insertSelect()
855 FirstReg = MRI.createVirtualRegister(FirstRC); in insertSelect()
856 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) in insertSelect()
861 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringMIPS32.cpp1935 const auto FirstReg = in legalizeMov() local
1939 SrcGPRHi = Target->makeReg(IceType_i32, FirstReg); in legalizeMov()
2007 const auto FirstReg = in legalizeMov() local
2011 Variable *SrcGPRHi = Target->makeReg(IceType_i32, FirstReg); in legalizeMov()
2094 const auto FirstReg = in legalizeMov() local
2098 Variable *DstGPRHi = Target->makeReg(IceType_i32, FirstReg); in legalizeMov()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp3992 unsigned FirstReg = Reg; in parseVectorList() local
3996 FirstReg = Reg = getDRegFromQReg(Reg); in parseVectorList()
4138 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
4140 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, in parseVectorList()
4150 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
4152 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, in parseVectorList()
4157 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, in parseVectorList()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp3707 unsigned FirstReg = Reg; in parseVectorList() local
3711 FirstReg = Reg = getDRegFromQReg(Reg); in parseVectorList()
3853 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
3856 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, in parseVectorList()
3866 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
3868 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, in parseVectorList()
3873 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, in parseVectorList()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp3139 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandTrunc() local
3156 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
3164 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()

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