| /external/vixl/examples/aarch64/ |
| D | neon-matrix-multiply.cc | 51 __ Fmul(v_out, v4.V4S(), v_in, 0); // e.g. (v0.V4S(), v4.V4S(), v8.S(), 0). in GenerateMultiplyColumn() local
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| /external/swiftshader/third_party/subzero/crosstest/ |
| D | test_arith.def | 46 X(Fmul, *, ) \
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInst.def | 41 X(Fmul, "fmul", 1) \
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| D | IceConverter.cpp | 301 return convertArithInstruction(Instr, Ice::InstArithmetic::Fmul); in convertInstruction()
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| D | IceTargetLoweringARM32.cpp | 2911 case InstArithmetic::Fmul: in lowerInt64Arithmetic()
3106 case InstArithmetic::Fmul: in lowerArithmetic()
3191 case InstArithmetic::Fmul: { in lowerArithmetic()
3512 case InstArithmetic::Fmul: in lowerArithmetic()
6944 case InstArithmetic::Fmul: in shouldTrackProducer()
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| D | WasmTranslator.cpp | 432 Control()->appendInst(InstArithmetic::create(Func, InstArithmetic::Fmul, in Binop()
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| D | IceTargetLoweringX86BaseImpl.h | 2059 case InstArithmetic::Fmul:
2205 case InstArithmetic::Fmul: {
2535 case InstArithmetic::Fmul:
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| D | PNaClTranslator.cpp | 1780 Op = Ice::InstArithmetic::Fmul; in convertBinopOpcode()
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| D | IceTargetLoweringMIPS32.cpp | 2736 case InstArithmetic::Fmul: in lowerInt64Arithmetic()
3018 case InstArithmetic::Fmul: in lowerArithmetic()
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| /external/v8/src/wasm/baseline/arm64/ |
| D | liftoff-assembler-arm64.h | 420 FP32_BINOP(f32_mul, Fmul) in I32_BINOP()
433 FP64_BINOP(f64_mul, Fmul) in I32_BINOP()
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 10865 __ Fmul(s0, s17, s18); in TEST() local
10866 __ Fmul(s1, s18, s19); in TEST() local
10867 __ Fmul(s2, s14, s14); in TEST() local
10868 __ Fmul(s3, s15, s20); in TEST() local
10869 __ Fmul(s4, s16, s20); in TEST() local
10870 __ Fmul(s5, s15, s19); in TEST() local
10871 __ Fmul(s6, s19, s16); in TEST() local
10873 __ Fmul(d7, d30, d31); in TEST() local
10874 __ Fmul(d8, d29, d31); in TEST() local
10875 __ Fmul(d9, d26, d26); in TEST() local
[all …]
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| D | test-disasm-aarch64.cc | 5000 COMPARE_MACRO(Fmul(v22.V8H(), v23.V8H(), v24.V8H()), in TEST()
5002 COMPARE_MACRO(Fmul(v25.V4H(), v26.V4H(), v27.V4H()), in TEST()
5100 COMPARE_MACRO(Fmul(v6.M, v7.M, v8.M), "fmul v6." S ", v7." S ", v8." S); in TEST()
5538 COMPARE_MACRO(Fmul(v0.V4H(), v1.V4H(), v2.H(), 0), in TEST()
5540 COMPARE_MACRO(Fmul(v2.V8H(), v3.V8H(), v15.H(), 3), in TEST()
5542 COMPARE_MACRO(Fmul(v0.V2S(), v1.V2S(), v2.S(), 0), in TEST()
5544 COMPARE_MACRO(Fmul(v2.V4S(), v3.V4S(), v15.S(), 3), in TEST()
5546 COMPARE_MACRO(Fmul(v0.V2D(), v1.V2D(), v2.D(), 0), in TEST()
5548 COMPARE_MACRO(Fmul(d0, d1, v2.D(), 0), "fmul d0, d1, v2.d[0]"); in TEST()
5549 COMPARE_MACRO(Fmul(s0, s1, v2.S(), 0), "fmul s0, s1, v2.s[0]"); in TEST()
[all …]
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 1313 __ Fmul(i.OutputFloat32Register(), i.InputFloat32Register(0), in AssembleArchInstruction() local
1348 __ Fmul(i.OutputDoubleRegister(), i.InputDoubleRegister(0), in AssembleArchInstruction() local
1745 SIMD_BINOP_CASE(kArm64F32x4Mul, Fmul, 4S); in AssembleArchInstruction()
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| /external/v8/src/arm64/ |
| D | macro-assembler-arm64.h | 247 V(fmul, Fmul) \
931 inline void Fmul(const VRegister& fd, const VRegister& fn,
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| D | macro-assembler-arm64-inl.h | 695 void TurboAssembler::Fmul(const VRegister& fd, const VRegister& fn, in Fmul() function
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| /external/v8/src/builtins/arm64/ |
| D | builtins-arm64.cc | 3059 __ Fmul(scratch1_double, scratch1_double, scratch1_double); in Generate_MathPowInternal() local
3065 __ Fmul(result_double, result_double, scratch1_double); in Generate_MathPowInternal() local
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 1544 void Fmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) { in Fmul() function
2776 V(fmul, Fmul) \
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2592 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); in ExpandLegalINT_TO_FP() local
2595 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); in ExpandLegalINT_TO_FP()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2411 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); in ExpandLegalINT_TO_FP() local
2414 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); in ExpandLegalINT_TO_FP()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2445 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); in ExpandLegalINT_TO_FP() local
2448 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); in ExpandLegalINT_TO_FP()
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| /external/swiftshader/src/Reactor/ |
| D | SubzeroReactor.cpp | 708 case Ice::InstArithmetic::Fmul: in isCommutative()
768 return createArithmetic(Ice::InstArithmetic::Fmul, lhs, rhs); in createFMul()
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