| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenHwModes.h | 28 struct HwMode { struct
29 HwMode(Record *R);
48 const HwMode &getMode(unsigned Id) const { in getMode() argument
59 std::vector<HwMode> Modes;
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| D | CodeGenHwModes.cpp | 22 HwMode::HwMode(Record *R) { in HwMode() function in HwMode
28 void HwMode::dump() const { in dump()
97 for (const HwMode &M : Modes) { in dump()
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| D | SubtargetEmitter.cpp | 1624 const HwMode &HM = CGH.getMode(M); in EmitHwModeCheck()
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| D | CodeGenDAGPatterns.cpp | 4163 const HwMode &HM = CGH.getMode(M); in ExpandHwModeBasedTypes()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/ |
| D | HwModeSelect.td | 21 def TestMode1 : HwMode<"+feat1">;
22 def TestMode2 : HwMode<"+feat2">;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVRegisterInfo.cpp | 30 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) in RISCVRegisterInfo() argument
32 /*PC*/0, HwMode) {} in RISCVRegisterInfo()
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| D | RISCV.td | 55 def RV64 : HwMode<"+64bit">;
56 def RV32 : HwMode<"-64bit">;
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| D | RISCVRegisterInfo.h | 26 RISCVRegisterInfo(unsigned HwMode);
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.h | 32 HexagonRegisterInfo(unsigned HwMode);
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| D | HexagonRegisterInfo.cpp | 45 HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) in HexagonRegisterInfo() argument
47 0/*PC*/, HwMode) {} in HexagonRegisterInfo()
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| D | Hexagon.td | 82 def Hvx64: HwMode<"+hvx-length64b">;
83 def Hvx128: HwMode<"+hvx-length128b">;
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 237 unsigned HwMode; variable
672 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; in getRegClassInfo()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 53 RCInfos(RCIs), HwMode(Mode) { in TargetRegisterInfo()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
| D | Target.td | 24 class HwMode<string FS> {
37 def DefaultMode : HwMode<"">;
44 class HwModeSelect<list<HwMode> Ms> {
45 list<HwMode> Modes = Ms;
53 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts>
68 class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []>
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterInfo.inc | 3728 unsigned PC = 0, unsigned HwMode = 0);
7304 unsigned PC, unsigned HwMode)
7307 LaneBitmask(0xFFFFFF80), RegClassInfos, HwMode) {
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 3875 unsigned PC = 0, unsigned HwMode = 0);
7757 unsigned PC, unsigned HwMode)
7760 LaneBitmask(0xFFFFFFE0), RegClassInfos, HwMode) {
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterInfo.inc | 3298 unsigned PC = 0, unsigned HwMode = 0);
13677 unsigned PC, unsigned HwMode)
13680 LaneBitmask(0xFFFFFFFF), RegClassInfos, HwMode) {
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 4979 unsigned PC = 0, unsigned HwMode = 0);
19279 unsigned PC, unsigned HwMode)
19282 LaneBitmask(0xFFFFFFB6), RegClassInfos, HwMode) {
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