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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dselect-mmx.ll3 ; RUN: llc -mtriple=i686-unknown-unknown -mattr=+mmx < %s | FileCheck %s --check-prefix=I32
26 ; I32-LABEL: test47:
27 ; I32: # %bb.0:
28 ; I32-NEXT: pushl %ebp
29 ; I32-NEXT: .cfi_def_cfa_offset 8
30 ; I32-NEXT: .cfi_offset %ebp, -8
31 ; I32-NEXT: movl %esp, %ebp
32 ; I32-NEXT: .cfi_def_cfa_register %ebp
33 ; I32-NEXT: andl $-8, %esp
34 ; I32-NEXT: subl $16, %esp
[all …]
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrMemory.td61 def LOAD_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
64 def LOAD_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
67 def LOAD_F32 : I<(outs F32:$dst), (ins i32imm:$off, I32:$addr,
70 def LOAD_F64 : I<(outs F64:$dst), (ins i32imm:$off, I32:$addr,
77 def : Pat<(i32 (load I32:$addr)), (LOAD_I32 0, $addr, 0)>;
78 def : Pat<(i64 (load I32:$addr)), (LOAD_I64 0, $addr, 0)>;
79 def : Pat<(f32 (load I32:$addr)), (LOAD_F32 0, $addr, 0)>;
80 def : Pat<(f64 (load I32:$addr)), (LOAD_F64 0, $addr, 0)>;
83 def : Pat<(i32 (load (regPlusImm I32:$addr, imm:$off))),
85 def : Pat<(i64 (load (regPlusImm I32:$addr, imm:$off))),
[all …]
DWebAssemblyInstrInteger.td59 def EQZ_I32 : I<(outs I32:$dst), (ins I32:$src),
60 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
62 def EQZ_I64 : I<(outs I32:$dst), (ins I64:$src),
63 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
69 def : Pat<(rotl I32:$lhs, (and I32:$rhs, 31)), (ROTL_I32 I32:$lhs, I32:$rhs)>;
70 def : Pat<(rotr I32:$lhs, (and I32:$rhs, 31)), (ROTR_I32 I32:$lhs, I32:$rhs)>;
76 def SELECT_I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs, I32:$cond),
77 [(set I32:$dst, (select I32:$cond, I32:$lhs, I32:$rhs))],
79 def SELECT_I64 : I<(outs I64:$dst), (ins I64:$lhs, I64:$rhs, I32:$cond),
80 [(set I64:$dst, (select I32:$cond, I64:$lhs, I64:$rhs))],
[all …]
DWebAssemblyInstrFormats.td33 def _I32 : I<(outs I32:$dst), (ins I32:$src),
34 [(set I32:$dst, (node I32:$src))],
41 def _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs),
42 [(set I32:$dst, (node I32:$lhs, I32:$rhs))],
65 def _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs),
66 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
68 def _I64 : I<(outs I32:$dst), (ins I64:$lhs, I64:$rhs),
69 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))],
73 def _F32 : I<(outs I32:$dst), (ins F32:$lhs, F32:$rhs),
74 [(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))],
[all …]
DWebAssemblyInstrConv.td18 def I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src),
19 [(set I32:$dst, (trunc I64:$src))],
22 def I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src),
23 [(set I64:$dst, (sext I32:$src))],
25 def I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src),
26 [(set I64:$dst, (zext I32:$src))],
34 def : Pat<(i64 (anyext I32:$src)), (I64_EXTEND_U_I32 I32:$src)>;
40 def I32_TRUNC_S_F32 : I<(outs I32:$dst), (ins F32:$src),
41 [(set I32:$dst, (fp_to_sint F32:$src))],
43 def I32_TRUNC_U_F32 : I<(outs I32:$dst), (ins F32:$src),
[all …]
DWebAssemblyInstrFloat.td80 def SELECT_F32 : I<(outs F32:$dst), (ins F32:$lhs, F32:$rhs, I32:$cond),
81 [(set F32:$dst, (select I32:$cond, F32:$lhs, F32:$rhs))],
83 def SELECT_F64 : I<(outs F64:$dst), (ins F64:$lhs, F64:$rhs, I32:$cond),
84 [(set F64:$dst, (select I32:$cond, F64:$lhs, F64:$rhs))],
92 def : Pat<(select (i32 (setne I32:$cond, 0)), F32:$lhs, F32:$rhs),
93 (SELECT_F32 F32:$lhs, F32:$rhs, I32:$cond)>;
94 def : Pat<(select (i32 (setne I32:$cond, 0)), F64:$lhs, F64:$rhs),
95 (SELECT_F64 F64:$lhs, F64:$rhs, I32:$cond)>;
98 def : Pat<(select (i32 (seteq I32:$cond, 0)), F32:$lhs, F32:$rhs),
99 (SELECT_F32 F32:$rhs, F32:$lhs, I32:$cond)>;
[all …]
DWebAssemblyInstrControl.td19 def BR_IF : I<(outs), (ins bb_op:$dst, I32:$cond),
20 [(brcond I32:$cond, bb:$dst)],
23 def BR_UNLESS : I<(outs), (ins bb_op:$dst, I32:$cond), [],
34 def : Pat<(brcond (i32 (setne I32:$cond, 0)), bb:$dst),
35 (BR_IF bb_op:$dst, I32:$cond)>;
36 def : Pat<(brcond (i32 (seteq I32:$cond, 0)), bb:$dst),
37 (BR_UNLESS bb_op:$dst, I32:$cond)>;
47 def BR_TABLE_I32 : I<(outs), (ins I32:$index, variable_ops),
48 [(WebAssemblybr_table I32:$index)],
82 defm : RETURN<I32>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td59 defm EQZ_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
60 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
62 defm EQZ_I64 : I<(outs I32:$dst), (ins I64:$src), (outs), (ins),
63 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
69 def : Pat<(rotl I32:$lhs, (and I32:$rhs, 31)), (ROTL_I32 I32:$lhs, I32:$rhs)>;
70 def : Pat<(rotr I32:$lhs, (and I32:$rhs, 31)), (ROTR_I32 I32:$lhs, I32:$rhs)>;
76 defm SELECT_I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs, I32:$cond),
78 [(set I32:$dst, (select I32:$cond, I32:$lhs, I32:$rhs))],
80 defm SELECT_I64 : I<(outs I64:$dst), (ins I64:$lhs, I64:$rhs, I32:$cond),
82 [(set I64:$dst, (select I32:$cond, I64:$lhs, I64:$rhs))],
[all …]
DWebAssemblyInstrConv.td18 defm I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src), (outs), (ins),
19 [(set I32:$dst, (trunc I64:$src))],
22 defm I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins),
23 [(set I64:$dst, (sext I32:$src))],
26 defm I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins),
27 [(set I64:$dst, (zext I32:$src))],
32 defm I32_EXTEND8_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
33 [(set I32:$dst, (sext_inreg I32:$src, i8))],
36 defm I32_EXTEND16_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
37 [(set I32:$dst, (sext_inreg I32:$src, i16))],
[all …]
DWebAssemblyInstrFormats.td80 defm _I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
81 [(set I32:$dst, (node I32:$src))],
91 defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins),
92 [(set I32:$dst, (node I32:$lhs, I32:$rhs))],
149 defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins),
150 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
153 defm _I64 : I<(outs I32:$dst), (ins I64:$lhs, I64:$rhs), (outs), (ins),
154 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))],
159 defm _F32 : I<(outs I32:$dst), (ins F32:$lhs, F32:$rhs), (outs), (ins),
160 [(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))],
[all …]
DWebAssemblyInstrMemory.td61 (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
70 defm LOAD_I32 : WebAssemblyLoad<I32, "i32.load", 0x28>;
79 Pat<(ty (kind I32:$addr)), (inst 0, 0, I32:$addr)>;
91 Pat<(ty (kind (operand I32:$addr, imm:$off))), (inst 0, imm:$off, I32:$addr)>;
103 Pat<(ty (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)))),
104 (inst 0, tglobaladdr:$off, I32:$addr)>;
112 Pat<(ty (kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)))),
113 (inst 0, texternalsym:$off, I32:$addr)>;
149 defm LOAD8_S_I32 : WebAssemblyLoad<I32, "i32.load8_s", 0x2c>;
150 defm LOAD8_U_I32 : WebAssemblyLoad<I32, "i32.load8_u", 0x2d>;
[all …]
DWebAssemblyInstrExceptRef.td18 (ins EXCEPT_REF:$lhs, EXCEPT_REF:$rhs, I32:$cond),
21 (select I32:$cond, EXCEPT_REF:$lhs,
28 def : Pat<(select (i32 (setne I32:$cond, 0)), EXCEPT_REF:$lhs, EXCEPT_REF:$rhs),
29 (SELECT_EXCEPT_REF EXCEPT_REF:$lhs, EXCEPT_REF:$rhs, I32:$cond)>;
30 def : Pat<(select (i32 (seteq I32:$cond, 0)), EXCEPT_REF:$lhs, EXCEPT_REF:$rhs),
31 (SELECT_EXCEPT_REF EXCEPT_REF:$rhs, EXCEPT_REF:$lhs, I32:$cond)>;
DWebAssemblyRuntimeLibcallSignatures.cpp498 Subtarget.hasAddr64() ? wasm::ValType::I64 : wasm::ValType::I32; in GetSignature()
514 Params.push_back(wasm::ValType::I32); in GetSignature()
522 Params.push_back(wasm::ValType::I32); in GetSignature()
534 Params.push_back(wasm::ValType::I32); in GetSignature()
541 Rets.push_back(wasm::ValType::I32); in GetSignature()
545 Rets.push_back(wasm::ValType::I32); in GetSignature()
549 Rets.push_back(wasm::ValType::I32); in GetSignature()
550 Params.push_back(wasm::ValType::I32); in GetSignature()
572 Params.push_back(wasm::ValType::I32); in GetSignature()
587 Params.push_back(wasm::ValType::I32); in GetSignature()
[all …]
DWebAssemblyInstrFloat.td80 defm SELECT_F32 : I<(outs F32:$dst), (ins F32:$lhs, F32:$rhs, I32:$cond),
82 [(set F32:$dst, (select I32:$cond, F32:$lhs, F32:$rhs))],
84 defm SELECT_F64 : I<(outs F64:$dst), (ins F64:$lhs, F64:$rhs, I32:$cond),
86 [(set F64:$dst, (select I32:$cond, F64:$lhs, F64:$rhs))],
94 def : Pat<(select (i32 (setne I32:$cond, 0)), F32:$lhs, F32:$rhs),
95 (SELECT_F32 F32:$lhs, F32:$rhs, I32:$cond)>;
96 def : Pat<(select (i32 (setne I32:$cond, 0)), F64:$lhs, F64:$rhs),
97 (SELECT_F64 F64:$lhs, F64:$rhs, I32:$cond)>;
100 def : Pat<(select (i32 (seteq I32:$cond, 0)), F32:$lhs, F32:$rhs),
101 (SELECT_F32 F32:$rhs, F32:$lhs, I32:$cond)>;
[all …]
DWebAssemblyInstrControl.td19 defm BR_IF : I<(outs), (ins bb_op:$dst, I32:$cond),
21 [(brcond I32:$cond, bb:$dst)],
24 defm BR_UNLESS : I<(outs), (ins bb_op:$dst, I32:$cond),
35 def : Pat<(brcond (i32 (setne I32:$cond, 0)), bb:$dst),
36 (BR_IF bb_op:$dst, I32:$cond)>;
37 def : Pat<(brcond (i32 (seteq I32:$cond, 0)), bb:$dst),
38 (BR_UNLESS bb_op:$dst, I32:$cond)>;
50 def BR_TABLE_I32 : NI<(outs), (ins I32:$index, variable_ops),
51 [(WebAssemblybr_table I32:$index)], 0,
56 def BR_TABLE_I32_S : NI<(outs), (ins I32:$index),
[all …]
DWebAssemblyInstrAtomics.td20 defm ATOMIC_LOAD_I32 : WebAssemblyLoad<I32, "i32.atomic.load", 0xfe10>;
58 defm ATOMIC_LOAD8_U_I32 : WebAssemblyLoad<I32, "i32.atomic.load8_u", 0xfe12>;
59 defm ATOMIC_LOAD16_U_I32 : WebAssemblyLoad<I32, "i32.atomic.load16_u", 0xfe13>;
196 defm ATOMIC_STORE_I32 : WebAssemblyStore<I32, "i32.atomic.store", 0xfe17>;
209 Pat<(kind I32:$addr, ty:$val), (inst 0, 0, I32:$addr, ty:$val)>;
217 Pat<(kind (operand I32:$addr, imm:$off), ty:$val),
218 (inst 0, imm:$off, I32:$addr, ty:$val)>;
225 Pat<(kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
227 (inst 0, tglobaladdr:$off, I32:$addr, ty:$val)>;
232 Pat<(kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)), ty:$val),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonPatterns.td355 def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>;
357 def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>;
360 def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>;
362 def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>;
378 def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>;
379 def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>;
400 def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>;
401 def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>;
419 def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>;
420 def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>;
[all …]
DHexagonIntrinsics.td21 : Pat <(IntID I32:$Rs),
22 (MI I32:$Rs)>;
34 : Pat<(IntID I32:$Rs, ImmPred:$It),
35 (MI I32:$Rs, ImmPred:$It)>;
39 : Pat<(IntID ImmPred:$Is, I32:$Rt),
40 (MI ImmPred:$Is, I32:$Rt)>;
47 : Pat<(IntID I32:$Rs, I64:$Rt),
48 (MI I32:$Rs, I64:$Rt)>;
51 : Pat <(IntID I32:$Rs, I32:$Rt),
52 (MI I32:$Rs, I32:$Rt)>;
[all …]
DHexagonPatternsHVX.td101 def: Pat<(ResType (Load I32:$Rt)),
102 (MI I32:$Rt, 0)>;
103 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))),
104 (MI I32:$Rt, imm:$s)>;
117 def: Pat<(ResType (Load (valignaddr I32:$Rt))),
118 (MI I32:$Rt, 0)>;
119 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
120 (MI I32:$Rt, imm:$Off)>;
143 def: Pat<(Store Value:$Vs, I32:$Rt),
144 (MI I32:$Rt, 0, Value:$Vs)>;
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td21 : Pat <(IntID I32:$Rs),
22 (MI I32:$Rs)>;
34 : Pat<(IntID I32:$Rs, ImmPred:$It),
35 (MI I32:$Rs, ImmPred:$It)>;
39 : Pat<(IntID ImmPred:$Is, I32:$Rt),
40 (MI ImmPred:$Is, I32:$Rt)>;
47 : Pat<(IntID I32:$Rs, I64:$Rt),
48 (MI I32:$Rs, I64:$Rt)>;
51 : Pat <(IntID I32:$Rs, I32:$Rt),
52 (MI I32:$Rs, I32:$Rt)>;
[all …]
/external/libxaac/decoder/armv7/
Dixheaacd_dec_DCT2_64_asm.s96 VSUB.I32 Q11, Q3, Q1
98 VADD.I32 Q10, Q3, Q1
100 VSUB.I32 Q9, Q0, Q2
102 VADD.I32 Q8, Q0, Q2
126 VADD.I32 Q13, Q8, Q15
128 VADD.I32 Q12, Q11, Q14
132 VSUB.I32 Q7, Q14, Q11
135 VSUB.I32 Q6, Q8, Q15
143 VSUB.I32 Q11, Q3, Q1
145 VADD.I32 Q10, Q3, Q1
[all …]
Dixheaacd_dct3_32.s65 VADD.I32 Q2, Q1, Q0
81 VSUB.I32 Q5, Q3, Q4
103 VADD.I32 Q2, Q1, Q0
125 VSUB.I32 Q5, Q3, Q4
158 VADD.I32 Q2, Q1, Q0
166 VSUB.I32 Q5, Q3, Q4
203 VADD.I32 Q2, Q1, Q0
217 VSUB.I32 Q5, Q3, Q4
243 VSUB.I32 D2, D2, D4
287 VADD.I32 D14, D11, D28
[all …]
Dixheaacd_post_twiddle.s131 VADD.I32 Q14, Q14, Q13
132 VSUB.I32 Q15, Q15, Q12
163 VADD.I32 Q11, Q11, Q8
166 VSUB.I32 Q10, Q9, Q10
188 VADD.I32 Q7, Q15, Q1
189 VADD.I32 Q13, Q14, Q0
202 VADD.I32 Q12, Q10, Q2
210 VADD.I32 Q8, Q11, Q8
238 VADD.I32 Q14, Q14, Q13
239 VSUB.I32 Q15, Q15, Q12
[all …]
Dixheaacd_pre_twiddle_compute.s139 VADD.I32 Q14, Q13, Q14
141 VSUB.I32 Q15, Q15, Q12
165 VADD.I32 Q10, Q10, Q9
170 VSUB.I32 Q11, Q8, Q11
208 VADD.I32 Q14, Q13, Q14
210 VSUB.I32 Q15, Q15, Q12
234 VADD.I32 Q10, Q10, Q9
239 VSUB.I32 Q11, Q8, Q11
272 VADD.I32 Q14, Q13, Q14
274 VSUB.I32 Q15, Q15, Q12
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/WebAssembly/
Dlibcall.ll22 ; CHECK-NEXT: - I32
23 ; CHECK-NEXT: - I32
25 ; CHECK-NEXT: ReturnType: I32
27 ; CHECK-NEXT: - I32
28 ; CHECK-NEXT: - I32
29 ; CHECK-NEXT: - I32

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