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Searched refs:INSVE (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsISelLowering.h192 INSVE, // Copy element from one vector to another enumerator
DMipsSEISelLowering.cpp1947 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
DMipsISelLowering.cpp220 case MipsISD::INSVE: return "MipsISD::INSVE"; in getTargetNodeName()
DMipsMSAInstrInfo.td56 def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.h238 INSVE, // Copy element from one vector to another enumerator
DMipsSEISelLowering.cpp1941 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
DMipsISelLowering.cpp298 case MipsISD::INSVE: return "MipsISD::INSVE"; in getTargetNodeName()
DMipsMSAInstrInfo.td48 def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
/external/v8/src/mips/
Dconstants-mips.h951 INSVE = (5U << 22), enumerator
Dassembler-mips.cc3670 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_B, n, ws, wd); in insve_b()
3674 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_H, n, ws, wd); in insve_h()
3678 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_W, n, ws, wd); in insve_w()
3682 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_D, n, ws, wd); in insve_d()
Ddisasm-mips.cc2180 case INSVE: in DecodeTypeMsaELM()
Dsimulator-mips.cc4683 case INSVE: in DecodeTypeMsaELM()
/external/v8/src/mips64/
Dconstants-mips64.h985 INSVE = (5U << 22), enumerator
Dassembler-mips64.cc3996 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_B, n, ws, wd); in insve_b()
4000 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_H, n, ws, wd); in insve_h()
4004 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_W, n, ws, wd); in insve_w()
4008 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_D, n, ws, wd); in insve_d()
Ddisasm-mips64.cc2494 case INSVE: in DecodeTypeMsaELM()
Dsimulator-mips64.cc4908 case INSVE: in DecodeTypeMsaELM()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenDAGISel.inc28581 /* 53663*/ /*SwitchOpcode*/ 4|128,1/*132*/, TARGET_VAL(MipsISD::INSVE),// ->53799