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Searched refs:ISL_AUX_USAGE_HIZ (Results 1 – 11 of 11) sorted by relevance

/external/mesa3d/src/intel/isl/
Disl_emit_depth_stencil.c115 if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) { in isl_genX()
157 info->hiz_usage == ISL_AUX_USAGE_HIZ); in isl_genX()
158 if (info->hiz_usage == ISL_AUX_USAGE_HIZ) { in isl_genX()
Disl_surface_state.c88 [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
96 [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
578 if (info->aux_usage == ISL_AUX_USAGE_HIZ) { in isl_genX()
630 if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ) in isl_genX()
Disl.h582 ISL_AUX_USAGE_HIZ, enumerator
/external/mesa3d/src/mesa/drivers/dri/i965/
Dintel_mipmap_tree.c378 mt->aux_usage = ISL_AUX_USAGE_HIZ; in intel_miptree_choose_aux_usage()
1828 assert(mt->aux_usage == ISL_AUX_USAGE_HIZ); in intel_miptree_alloc_hiz()
1874 case ISL_AUX_USAGE_HIZ: in intel_miptree_alloc_aux()
2309 assert(aux_usage == ISL_AUX_USAGE_NONE || aux_usage == ISL_AUX_USAGE_HIZ); in intel_miptree_prepare_hiz_access()
2315 if (aux_usage != ISL_AUX_USAGE_HIZ || !fast_clear_supported) in intel_miptree_prepare_hiz_access()
2320 if (aux_usage != ISL_AUX_USAGE_HIZ) in intel_miptree_prepare_hiz_access()
2329 if (aux_usage == ISL_AUX_USAGE_HIZ) in intel_miptree_prepare_hiz_access()
2364 assert(aux_usage == ISL_AUX_USAGE_NONE || aux_usage == ISL_AUX_USAGE_HIZ); in intel_miptree_finish_hiz_write()
2368 assert(aux_usage == ISL_AUX_USAGE_HIZ); in intel_miptree_finish_hiz_write()
2375 assert(aux_usage == ISL_AUX_USAGE_HIZ); in intel_miptree_finish_hiz_write()
[all …]
Dbrw_blorp.c163 if (surf->aux_usage == ISL_AUX_USAGE_HIZ && in blorp_surf_for_miptree()
184 assert(surf->aux_usage == ISL_AUX_USAGE_HIZ); in blorp_surf_for_miptree()
313 if (src_aux_usage == ISL_AUX_USAGE_HIZ) in brw_blorp_blit_miptrees()
1612 assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->hiz_buf); in intel_hiz_exec()
1616 blorp_surf_for_miptree(brw, &surf, mt, ISL_AUX_USAGE_HIZ, true, in intel_hiz_exec()
Dbrw_wm_surface_state.c165 case ISL_AUX_USAGE_HIZ: in brw_emit_surface_state()
/external/mesa3d/src/intel/vulkan/
Danv_image.c404 image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ; in make_surface()
819 return ISL_AUX_USAGE_HIZ; in anv_layout_to_aux_usage()
852 return ISL_AUX_USAGE_HIZ; in anv_layout_to_aux_usage()
931 if (device->info.gen >= 9 && aux_usage == ISL_AUX_USAGE_HIZ) in anv_image_fill_surface_state()
DgenX_cmd_buffer.c381 if (image->planes[0].aux_usage != ISL_AUX_USAGE_HIZ || initial_layout == final_layout) in transition_depth_buffer()
384 const bool hiz_enabled = ISL_AUX_USAGE_HIZ == in transition_depth_buffer()
387 const bool enable_hiz = ISL_AUX_USAGE_HIZ == in transition_depth_buffer()
1010 cmd_buffer->state.hiz_enabled = aux_usage == ISL_AUX_USAGE_HIZ; in genX()
2960 if (info.hiz_usage == ISL_AUX_USAGE_HIZ) { in cmd_buffer_emit_depth_stencil()
2990 cmd_buffer->state.hiz_enabled = info.hiz_usage == ISL_AUX_USAGE_HIZ; in cmd_buffer_emit_depth_stencil()
Danv_blorp.c200 aux_usage == ISL_AUX_USAGE_HIZ) in get_blorp_surf_for_anv_image()
1246 ISL_AUX_USAGE_HIZ; in anv_cmd_buffer_clear_subpass()
1655 image->planes[0].aux_usage != ISL_AUX_USAGE_HIZ) in anv_gen8_hiz_op_resolve()
1677 surf.aux_usage = ISL_AUX_USAGE_HIZ; in anv_gen8_hiz_op_resolve()
Dgen8_cmd_buffer.c330 assert(ds_iview && ds_iview->image->planes[0].aux_usage == ISL_AUX_USAGE_HIZ); in want_stencil_pma_fix()
/external/mesa3d/src/intel/blorp/
Dblorp_genX_exec.h1264 if (aux_usage == ISL_AUX_USAGE_HIZ) in blorp_emit_surface_state()
1458 if (info.hiz_usage == ISL_AUX_USAGE_HIZ) { in blorp_emit_depth_stencil_config()