1 /*
2 * Copyright 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdint.h>
25
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
28
29 static uint64_t
__gen_combine_address(void * data,void * loc,uint64_t addr,uint32_t delta)30 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
31 {
32 return addr + delta;
33 }
34
35 #include "genxml/gen_macros.h"
36 #include "genxml/genX_pack.h"
37
38 #include "isl_priv.h"
39
40 static const uint32_t isl_to_gen_ds_surftype[] = {
41 #if GEN_GEN >= 9
42 /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
43 *
44 * "If depth/stencil is enabled with 1D render target, depth/stencil
45 * surface type needs to be set to 2D surface type and height set to 1.
46 * Depth will use (legacy) TileY and stencil will use TileW. For this
47 * case only, the Surface Type of the depth buffer can be 2D while the
48 * Surface Type of the render target(s) are 1D, representing an
49 * exception to a programming note above.
50 */
51 [ISL_SURF_DIM_1D] = SURFTYPE_2D,
52 #else
53 [ISL_SURF_DIM_1D] = SURFTYPE_1D,
54 #endif
55 [ISL_SURF_DIM_2D] = SURFTYPE_2D,
56 [ISL_SURF_DIM_3D] = SURFTYPE_3D,
57 };
58
59 void
isl_genX(emit_depth_stencil_hiz_s)60 isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
61 const struct isl_depth_stencil_hiz_emit_info *restrict info)
62 {
63 struct GENX(3DSTATE_DEPTH_BUFFER) db = {
64 GENX(3DSTATE_DEPTH_BUFFER_header),
65 };
66
67 if (info->depth_surf) {
68 db.SurfaceType = isl_to_gen_ds_surftype[info->depth_surf->dim];
69 db.SurfaceFormat = isl_surf_get_depth_format(dev, info->depth_surf);
70 db.Width = info->depth_surf->logical_level0_px.width - 1;
71 db.Height = info->depth_surf->logical_level0_px.height - 1;
72 } else if (info->stencil_surf) {
73 db.SurfaceType = isl_to_gen_ds_surftype[info->stencil_surf->dim];
74 db.SurfaceFormat = D32_FLOAT;
75 db.Width = info->stencil_surf->logical_level0_px.width - 1;
76 db.Height = info->stencil_surf->logical_level0_px.height - 1;
77 } else {
78 db.SurfaceType = SURFTYPE_NULL;
79 db.SurfaceFormat = D32_FLOAT;
80 }
81
82 if (info->depth_surf || info->stencil_surf) {
83 /* These are based entirely on the view */
84 db.Depth = db.RenderTargetViewExtent = info->view->array_len - 1;
85 db.LOD = info->view->base_level;
86 db.MinimumArrayElement = info->view->base_array_layer;
87 }
88
89 if (info->depth_surf) {
90 #if GEN_GEN >= 7
91 db.DepthWriteEnable = true;
92 #endif
93 db.SurfaceBaseAddress = info->depth_address;
94 #if GEN_GEN >= 6
95 db.DepthBufferMOCS = info->mocs;
96 #endif
97
98 #if GEN_GEN <= 6
99 db.TiledSurface = info->depth_surf->tiling != ISL_TILING_LINEAR;
100 db.TileWalk = info->depth_surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
101 TILEWALK_XMAJOR;
102 db.MIPMapLayoutMode = MIPLAYOUT_BELOW;
103 #endif
104
105 db.SurfacePitch = info->depth_surf->row_pitch - 1;
106 #if GEN_GEN >= 8
107 db.SurfaceQPitch =
108 isl_surf_get_array_pitch_el_rows(info->depth_surf) >> 2;
109 #endif
110 }
111
112 #if GEN_GEN == 5 || GEN_GEN == 6
113 const bool separate_stencil =
114 info->stencil_surf && info->stencil_surf->format == ISL_FORMAT_R8_UINT;
115 if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) {
116 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
117 db.SeparateStencilBufferEnable = true;
118 db.HierarchicalDepthBufferEnable = true;
119 }
120 #endif
121
122 #if GEN_GEN >= 6
123 struct GENX(3DSTATE_STENCIL_BUFFER) sb = {
124 GENX(3DSTATE_STENCIL_BUFFER_header),
125 };
126 #else
127 # define sb db
128 #endif
129
130 if (info->stencil_surf) {
131 #if GEN_GEN >= 7
132 db.StencilWriteEnable = true;
133 #endif
134 #if GEN_GEN >= 8 || GEN_IS_HASWELL
135 sb.StencilBufferEnable = true;
136 #endif
137 sb.SurfaceBaseAddress = info->stencil_address;
138 #if GEN_GEN >= 6
139 sb.StencilBufferMOCS = info->mocs;
140 #endif
141 sb.SurfacePitch = info->stencil_surf->row_pitch - 1;
142 #if GEN_GEN >= 8
143 sb.SurfaceQPitch =
144 isl_surf_get_array_pitch_el_rows(info->stencil_surf) >> 2;
145 #endif
146 }
147
148 #if GEN_GEN >= 6
149 struct GENX(3DSTATE_HIER_DEPTH_BUFFER) hiz = {
150 GENX(3DSTATE_HIER_DEPTH_BUFFER_header),
151 };
152 struct GENX(3DSTATE_CLEAR_PARAMS) clear = {
153 GENX(3DSTATE_CLEAR_PARAMS_header),
154 };
155
156 assert(info->hiz_usage == ISL_AUX_USAGE_NONE ||
157 info->hiz_usage == ISL_AUX_USAGE_HIZ);
158 if (info->hiz_usage == ISL_AUX_USAGE_HIZ) {
159 db.HierarchicalDepthBufferEnable = true;
160
161 hiz.SurfaceBaseAddress = info->hiz_address;
162 hiz.HierarchicalDepthBufferMOCS = info->mocs;
163 hiz.SurfacePitch = info->hiz_surf->row_pitch - 1;
164 #if GEN_GEN >= 8
165 /* From the SKL PRM Vol2a:
166 *
167 * The interpretation of this field is dependent on Surface Type
168 * as follows:
169 * - SURFTYPE_1D: distance in pixels between array slices
170 * - SURFTYPE_2D/CUBE: distance in rows between array slices
171 * - SURFTYPE_3D: distance in rows between R - slices
172 *
173 * Unfortunately, the docs aren't 100% accurate here. They fail to
174 * mention that the 1-D rule only applies to linear 1-D images.
175 * Since depth and HiZ buffers are always tiled, they are treated as
176 * 2-D images. Prior to Sky Lake, this field is always in rows.
177 */
178 hiz.SurfaceQPitch =
179 isl_surf_get_array_pitch_sa_rows(info->hiz_surf) >> 2;
180 #endif
181
182 clear.DepthClearValueValid = true;
183 #if GEN_GEN >= 8
184 clear.DepthClearValue = info->depth_clear_value;
185 #else
186 switch (info->depth_surf->format) {
187 case ISL_FORMAT_R32_FLOAT: {
188 union { float f; uint32_t u; } fu;
189 fu.f = info->depth_clear_value;
190 clear.DepthClearValue = fu.u;
191 break;
192 }
193 case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
194 clear.DepthClearValue = info->depth_clear_value * ((1u << 24) - 1);
195 break;
196 case ISL_FORMAT_R16_UNORM:
197 clear.DepthClearValue = info->depth_clear_value * ((1u << 16) - 1);
198 break;
199 default:
200 unreachable("Invalid depth type");
201 }
202 #endif
203 }
204 #endif /* GEN_GEN >= 6 */
205
206 /* Pack everything into the batch */
207 uint32_t *dw = batch;
208 GENX(3DSTATE_DEPTH_BUFFER_pack)(NULL, dw, &db);
209 dw += GENX(3DSTATE_DEPTH_BUFFER_length);
210
211 #if GEN_GEN >= 6
212 GENX(3DSTATE_STENCIL_BUFFER_pack)(NULL, dw, &sb);
213 dw += GENX(3DSTATE_STENCIL_BUFFER_length);
214
215 GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &hiz);
216 dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length);
217
218 GENX(3DSTATE_CLEAR_PARAMS_pack)(NULL, dw, &clear);
219 dw += GENX(3DSTATE_CLEAR_PARAMS_length);
220 #endif
221 }
222