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Searched refs:ISL_TILING_LINEAR (Results 1 – 15 of 15) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dintel_blit.c146 if (mt->surf.tiling != ISL_TILING_LINEAR) in blt_pitch()
203 if (mt->surf.tiling == ISL_TILING_LINEAR) { in get_blit_intratile_offset_el()
476 if (tiling != ISL_TILING_LINEAR) in alignment_valid()
505 if (dst_tiling != ISL_TILING_LINEAR) in xy_blit_cmd()
508 if (src_tiling != ISL_TILING_LINEAR) in xy_blit_cmd()
568 assert(src_tiling == ISL_TILING_LINEAR || (src_pitch % src_tile_w) == 0); in intelEmitCopyBlit()
569 assert(dst_tiling == ISL_TILING_LINEAR || (dst_pitch % dst_tile_w) == 0); in intelEmitCopyBlit()
609 if (dst_tiling != ISL_TILING_LINEAR) in intelEmitCopyBlit()
612 if (src_tiling != ISL_TILING_LINEAR) in intelEmitCopyBlit()
663 if (dst_tiling != ISL_TILING_LINEAR) { in intelEmitImmediateColorExpandBlit()
[all …]
Dintel_pixel_draw.c121 ISL_TILING_LINEAR, in do_blit_drawpixels()
Dintel_mipmap_tree.c122 return tiling != ISL_TILING_LINEAR; in intel_tiling_supports_ccs()
517 if (tiling == ISL_TILING_LINEAR) in need_to_retile_as_linear()
608 init_info.tiling_flags = 1u << ISL_TILING_LINEAR; in make_surface()
622 if (mt->surf.tiling != ISL_TILING_LINEAR) in make_surface()
852 if (tiling != ISL_TILING_LINEAR) in intel_miptree_create_for_bo()
1387 case ISL_TILING_LINEAR: in intel_get_tile_dims()
1429 case ISL_TILING_LINEAR: in intel_miptree_get_aligned_offset()
3579 if (mt->surf.tiling != ISL_TILING_LINEAR && in use_intel_mipree_map_blit()
3720 return (devinfo->gen >= 9 && tiling == ISL_TILING_LINEAR ? in get_isl_dim_layout()
Dbrw_blorp.c954 ISL_TILING_LINEAR, 0); in brw_blorp_upload_miptree()
1076 ISL_TILING_LINEAR, 0); in brw_blorp_download_miptree()
/external/mesa3d/src/intel/isl/
Disl_drm.c37 case ISL_TILING_LINEAR: in isl_tiling_to_i915_tiling()
62 return ISL_TILING_LINEAR; in isl_tiling_from_i915_tiling()
78 .tiling = ISL_TILING_LINEAR,
Disl.c165 if (tiling != ISL_TILING_LINEAR && !isl_is_pow2(format_bpb)) { in isl_tiling_get_info()
178 case ISL_TILING_LINEAR: in isl_tiling_get_info()
368 CHOOSE(ISL_TILING_LINEAR); in isl_surf_choose_tiling()
376 CHOOSE(ISL_TILING_LINEAR); in isl_surf_choose_tiling()
632 if (tiling == ISL_TILING_LINEAR) in isl_surf_choose_dim_layout()
892 tile_info->tiling != ISL_TILING_LINEAR) { in isl_calc_array_pitch_el_rows_gen4_2d()
1225 if (tile_info->tiling != ISL_TILING_LINEAR) in isl_calc_row_pitch_alignment()
1295 if (tile_info->tiling == ISL_TILING_LINEAR) { in isl_calc_min_row_pitch()
1334 if (surf_info->row_pitch == 0 && tile_info->tiling == ISL_TILING_LINEAR) { in isl_calc_row_pitch()
1462 if (tiling == ISL_TILING_LINEAR) { in isl_surf_init_s()
[all …]
Disl_gen6.c59 if (tiling == ISL_TILING_LINEAR) in isl_gen6_choose_msaa_layout()
Disl_surface_state.c68 [ISL_TILING_LINEAR] = LINEAR,
444 s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR, in isl_genX()
521 assert(info->surf->tiling != ISL_TILING_LINEAR); in isl_genX()
Disl_gen7.c112 if (tiling == ISL_TILING_LINEAR) in isl_gen7_choose_msaa_layout()
Disl_emit_depth_stencil.c99 db.TiledSurface = info->depth_surf->tiling != ISL_TILING_LINEAR; in isl_genX()
Disl_storage_image.c258 case ISL_TILING_LINEAR: in isl_surf_fill_image_param()
Disl.h456 ISL_TILING_LINEAR = 0, enumerator
471 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
/external/mesa3d/src/intel/vulkan/
Danv_image.c919 assert(surface->isl.tiling == ISL_TILING_LINEAR); in anv_image_fill_surface_state()
920 assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR); in anv_image_fill_surface_state()
1016 assert(surface->isl.tiling == ISL_TILING_LINEAR); in anv_image_fill_surface_state()
DgenX_cmd_buffer.c626 assert(image->planes[plane].surface.isl.tiling == ISL_TILING_LINEAR); in transition_color_buffer()
627 assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR); in transition_color_buffer()
/external/mesa3d/src/intel/blorp/
Dblorp_clear.c406 if (surf->surf->tiling == ISL_TILING_LINEAR) in blorp_clear()