| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 519 unsigned ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); in mergeRead2Pair() local
520 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeRead2Pair()
527 .addReg(ImmReg) in mergeRead2Pair()
607 unsigned ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); in mergeWrite2Pair() local
608 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeWrite2Pair()
615 .addReg(ImmReg) in mergeWrite2Pair()
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| D | R600ISelLowering.cpp | 2155 unsigned ImmReg = R600::ALU_LITERAL_X; in FoldOperand() local
2162 ImmReg = R600::ZERO; in FoldOperand()
2164 ImmReg = R600::HALF; in FoldOperand()
2166 ImmReg = R600::ONE; in FoldOperand()
2174 ImmReg = R600::ZERO; in FoldOperand()
2176 ImmReg = R600::ONE_INT; in FoldOperand()
2185 if (ImmReg == R600::ALU_LITERAL_X) { in FoldOperand()
2194 Src = DAG.getRegister(ImmReg, MVT::i32); in FoldOperand()
|
| D | SIInstrInfo.cpp | 4490 unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
4495 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg) in movePackToVALU()
4499 .addReg(ImmReg, RegState::Kill) in movePackToVALU()
4509 unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
4510 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg) in movePackToVALU()
4513 .addReg(ImmReg, RegState::Kill) in movePackToVALU()
4519 unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
4524 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg) in movePackToVALU()
4528 .addReg(ImmReg, RegState::Kill) in movePackToVALU()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 2099 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); in PPCMaterializeInt() local
2101 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg); in PPCMaterializeInt()
2102 return ImmReg; in PPCMaterializeInt()
2119 unsigned ImmReg = createResultReg(RC); in PPCMaterializeInt() local
2120 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg) in PPCMaterializeInt()
2122 return ImmReg; in PPCMaterializeInt()
2273 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); in fastEmit_i() local
2275 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg); in fastEmit_i()
2276 return ImmReg; in fastEmit_i()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 2200 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); in PPCMaterializeInt() local
2202 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg); in PPCMaterializeInt()
2203 return ImmReg; in PPCMaterializeInt()
2220 unsigned ImmReg = createResultReg(RC); in PPCMaterializeInt() local
2221 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg) in PPCMaterializeInt()
2223 return ImmReg; in PPCMaterializeInt()
2381 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); in fastEmit_i() local
2383 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg); in fastEmit_i()
2384 return ImmReg; in fastEmit_i()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 2253 unsigned ImmReg = AMDGPU::ALU_LITERAL_X; in FoldOperand() local
2261 ImmReg = AMDGPU::ZERO; in FoldOperand()
2263 ImmReg = AMDGPU::HALF; in FoldOperand()
2265 ImmReg = AMDGPU::ONE; in FoldOperand()
2273 ImmReg = AMDGPU::ZERO; in FoldOperand()
2275 ImmReg = AMDGPU::ONE_INT; in FoldOperand()
2284 if (ImmReg == AMDGPU::ALU_LITERAL_X) { in FoldOperand()
2293 Src = DAG.getRegister(ImmReg, MVT::i32); in FoldOperand()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 483 unsigned ImmReg = createResultReg(RC); in ARMMaterializeInt() local
485 TII.get(Opc), ImmReg) in ARMMaterializeInt()
487 return ImmReg; in ARMMaterializeInt()
499 unsigned ImmReg = createResultReg(RC); in ARMMaterializeInt() local
501 TII.get(Opc), ImmReg) in ARMMaterializeInt()
503 return ImmReg; in ARMMaterializeInt()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 478 unsigned ImmReg = createResultReg(RC); in ARMMaterializeInt() local
480 TII.get(Opc), ImmReg) in ARMMaterializeInt()
482 return ImmReg; in ARMMaterializeInt()
494 unsigned ImmReg = createResultReg(RC); in ARMMaterializeInt() local
496 TII.get(Opc), ImmReg) in ARMMaterializeInt()
498 return ImmReg; in ARMMaterializeInt()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1433 unsigned ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL); in processBlock() local
1434 if (ImmReg) { in processBlock()
1435 HBS::replaceReg(DR, ImmReg, MRI); in processBlock()
1436 BT.put(ImmReg, BT.lookup(DR)); in processBlock()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1482 unsigned ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL); in processBlock() local
1483 if (ImmReg) { in processBlock()
1484 HBS::replaceReg(DR, ImmReg, MRI); in processBlock()
1485 BT.put(ImmReg, DRC); in processBlock()
|