/external/swiftshader/third_party/subzero/src/ |
D | IceConverter.cpp | 206 Ice::Operand *convertOperand(const Instruction *Instr, unsigned OpNum) { in convertOperand() argument 207 if (OpNum >= Instr->getNumOperands()) { in convertOperand() 210 const Value *Op = Instr->getOperand(OpNum); in convertOperand() 224 Ice::Inst *convertInstruction(const Instruction *Instr) { in convertInstruction() argument 225 switch (Instr->getOpcode()) { in convertInstruction() 227 return convertPHINodeInstruction(cast<PHINode>(Instr)); in convertInstruction() 229 return convertBrInstruction(cast<BranchInst>(Instr)); in convertInstruction() 231 return convertRetInstruction(cast<ReturnInst>(Instr)); in convertInstruction() 233 return convertIntToPtrInstruction(cast<IntToPtrInst>(Instr)); in convertInstruction() 235 return convertPtrToIntInstruction(cast<PtrToIntInst>(Instr)); in convertInstruction() [all …]
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D | IceInstrumentation.cpp | 61 Inst *Instr = iteratorToInst(Context.getCur()); in instrumentInst() local 62 switch (Instr->getKind()) { in instrumentInst() 64 instrumentAlloca(Context, llvm::cast<InstAlloca>(Instr)); in instrumentInst() 67 instrumentArithmetic(Context, llvm::cast<InstArithmetic>(Instr)); in instrumentInst() 70 instrumentBr(Context, llvm::cast<InstBr>(Instr)); in instrumentInst() 73 instrumentCall(Context, llvm::cast<InstCall>(Instr)); in instrumentInst() 76 instrumentCast(Context, llvm::cast<InstCast>(Instr)); in instrumentInst() 79 instrumentExtractElement(Context, llvm::cast<InstExtractElement>(Instr)); in instrumentInst() 82 instrumentFcmp(Context, llvm::cast<InstFcmp>(Instr)); in instrumentInst() 85 instrumentIcmp(Context, llvm::cast<InstIcmp>(Instr)); in instrumentInst() [all …]
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D | IceVariableSplitting.cpp | 80 for (const Inst &Instr : Node->getInsts()) { in reset() local 81 if (Instr.isDeleted()) in reset() 83 for (SizeT i = 0; i < Instr.getSrcSize(); ++i) { in reset() 84 if (auto *SrcVar = llvm::dyn_cast<Variable>(Instr.getSrc(i))) { in reset() 86 Map[VarNum].LastUseInst = &Instr; in reset() 141 bool isInstLastUseOfVar(const Variable *Var, const Inst *Instr) { in isInstLastUseOfVar() argument 142 return Map[getVarNum(Var)].LastUseInst == Instr; in isInstLastUseOfVar() 190 Instr = CurInst; in setInst() 191 Dest = Instr->getDest(); in setInst() 221 Instr->getNumber())) { in handleUnwantedInstruction() [all …]
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D | IceTargetLowering.cpp | 82 void LoweringContext::insert(Inst *Instr) { in insert() argument 83 getNode()->getInsts().insert(Next, Instr); in insert() 84 LastInserted = Instr; in insert() 111 Inst *Instr = LastInserted; in availabilityUpdate() local 112 if (Instr == nullptr) in availabilityUpdate() 114 if (!Instr->isVarAssign()) in availabilityUpdate() 117 LastDest = Instr->getDest(); in availabilityUpdate() 118 LastSrc = llvm::cast<Variable>(Instr->getSrc(0)); in availabilityUpdate() 404 Inst *Instr = iteratorToInst(Context.getCur()); in lower() local 405 Instr->deleteIfDead(); in lower() [all …]
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D | IceInst.h | 300 static bool classof(const Inst *Instr) { return Instr->getKind() == Alloca; } in classof() argument 338 static bool classof(const Inst *Instr) { in classof() argument 339 return Instr->getKind() == Arithmetic; in classof() 366 static bool classof(const Inst *Instr) { return Instr->getKind() == Assign; } in classof() argument 407 static bool classof(const Inst *Instr) { return Instr->getKind() == Br; } in classof() argument 447 static bool classof(const Inst *Instr) { return Instr->getKind() == Call; } in classof() argument 489 static bool classof(const Inst *Instr) { return Instr->getKind() == Cast; } in classof() argument 512 static bool classof(const Inst *Instr) { in classof() argument 513 return Instr->getKind() == ExtractElement; in classof() 544 static bool classof(const Inst *Instr) { return Instr->getKind() == Fcmp; } in classof() argument [all …]
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D | IceTargetLowering.h | 53 #define UnimplementedLoweringError(Target, Instr) \ argument 56 (Target)->addFakeDefUses(Instr); \ 61 (std::string("Not yet implemented: ") + Instr->getInstName()) \ 96 void insert(Inst *Instr); 224 void lowerInst(CfgNode *Node, InstList::iterator Next, InstHighLevel *Instr); 400 virtual void lowerAlloca(const InstAlloca *Instr) = 0; 401 virtual void lowerArithmetic(const InstArithmetic *Instr) = 0; 402 virtual void lowerAssign(const InstAssign *Instr) = 0; 403 virtual void lowerBr(const InstBr *Instr) = 0; 404 virtual void lowerBreakpoint(const InstBreakpoint *Instr) = 0; [all …]
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D | IceCfg.cpp | 282 for (auto &Instr : Node->getPhis()) { in fixPhiNodes() local 283 auto *Phi = llvm::cast<InstPhi>(&Instr); in fixPhiNodes() 560 size_t operator()(const Inst *Instr) const { in localCSE() 561 auto Kind = Instr->getKind(); in localCSE() 565 for (SizeT i = 0; i < Instr->getSrcSize(); ++i) { in localCSE() 566 Result ^= Instr->getSrc(i)->hashValue(); in localCSE() 618 for (Inst &Instr : Node->getInsts()) { in localCSE() 619 if (Instr.isDeleted() || !llvm::isa<InstArithmetic>(&Instr)) in localCSE() 623 auto Iter = Replacements.find(Instr.getDest()); in localCSE() 629 auto DepIter = Dependency.find(Instr.getDest()); in localCSE() [all …]
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D | IceTargetLoweringARM32.cpp | 447 void TargetARM32::genTargetHelperCallFor(Inst *Instr) { in genTargetHelperCallFor() argument 451 switch (Instr->getKind()) { in genTargetHelperCallFor() 455 Variable *Dest = Instr->getDest(); in genTargetHelperCallFor() 458 llvm::cast<InstArithmetic>(Instr)->getOp(); in genTargetHelperCallFor() 469 scalarizeArithmetic(Op, Dest, Instr->getSrc(0), Instr->getSrc(1)); in genTargetHelperCallFor() 470 Instr->setDeleted(); in genTargetHelperCallFor() 503 Call->addArg(Instr->getSrc(0)); in genTargetHelperCallFor() 504 Call->addArg(Instr->getSrc(1)); in genTargetHelperCallFor() 505 Instr->setDeleted(); in genTargetHelperCallFor() 541 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() [all …]
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D | IceTargetLoweringX86BaseImpl.h | 102 Inst *Instr = nullptr; 140 static BoolFoldingProducerKind getProducerKind(const Inst *Instr); 141 static BoolFoldingConsumerKind getConsumerKind(const Inst *Instr); 142 static bool hasComplexLowering(const Inst *Instr); 153 return Element != Producers.end() && Element->second.Instr != nullptr; 155 void setInvalid(SizeT VarNum) { Producers[VarNum].Instr = nullptr; } 156 void invalidateProducersOnStore(const Inst *Instr); 163 : Instr(I), IsComplex(BoolFolding<Traits>::hasComplexLowering(I)) {} 167 BoolFolding<Traits>::getProducerKind(const Inst *Instr) { 168 if (llvm::isa<InstIcmp>(Instr)) { [all …]
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D | IceTargetLoweringMIPS32.cpp | 210 for (Inst &Instr : Node->getInsts()) { in unsetIfNonLeafFunc() 211 if (llvm::isa<InstCall>(&Instr)) { in unsetIfNonLeafFunc() 265 void TargetMIPS32::genTargetHelperCallFor(Inst *Instr) { in genTargetHelperCallFor() argument 268 Variable *Dest = Instr->getDest(); in genTargetHelperCallFor() 271 switch (Instr->getKind()) { in genTargetHelperCallFor() 276 Operand *SrcT = llvm::cast<InstSelect>(Instr)->getTrueOperand(); in genTargetHelperCallFor() 277 Operand *SrcF = llvm::cast<InstSelect>(Instr)->getFalseOperand(); in genTargetHelperCallFor() 278 Operand *Cond = llvm::cast<InstSelect>(Instr)->getCondition(); in genTargetHelperCallFor() 299 Instr->setDeleted(); in genTargetHelperCallFor() 305 InstFcmp::FCond Cond = llvm::cast<InstFcmp>(Instr)->getCondition(); in genTargetHelperCallFor() [all …]
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D | IceInstARM32.h | 485 const InstARM32 *Instr, const Cfg *Func, 488 const InstARM32 *Instr, const Cfg *Func); 499 static bool isClassof(const Inst *Instr, InstKindARM32 MyKind) { in isClassof() argument 500 return Instr->getKind() == static_cast<InstKind>(MyKind); in isClassof() 526 static void emitUnaryopGPR(const char *Opcode, const InstARM32Pred *Instr, 529 const InstARM32Pred *Instr, const Cfg *Func); 530 static void emitTwoAddr(const char *Opcode, const InstARM32Pred *Instr, 532 static void emitThreeAddr(const char *Opcode, const InstARM32Pred *Instr, 534 static void emitFourAddr(const char *Opcode, const InstARM32Pred *Instr, 536 static void emitCmpLike(const char *Opcode, const InstARM32Pred *Instr, [all …]
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D | IceASanInstrumentation.cpp | 342 InstCall *Instr) { in instrumentCall() argument 344 llvm::dyn_cast<ConstantRelocatable>(Instr->getCallTarget()); in instrumentCall() 356 InstCall::create(Context.getNode()->getCfg(), Instr->getNumArgs(), in instrumentCall() 357 Instr->getDest(), NewFunc, Instr->isTailcall()); in instrumentCall() 358 for (SizeT I = 0, Args = Instr->getNumArgs(); I < Args; ++I) in instrumentCall() 359 NewCall->addArg(Instr->getArg(I)); in instrumentCall() 361 Instr->setDeleted(); in instrumentCall() 365 InstLoad *Instr) { in instrumentLoad() argument 366 Operand *Src = Instr->getSourceAddress(); in instrumentLoad() 369 Instr->getDest(), instrumentReloc(Reloc)); in instrumentLoad() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-cfi-verify/lib/ |
D | FileAnalysis.h | 78 struct Instr { struct 98 const Instr *getInstruction(uint64_t Address) const; 102 const Instr &getInstructionOrDie(uint64_t Address) const; 107 const Instr *getPrevInstructionSequential(const Instr &InstrMeta) const; 108 const Instr *getNextInstructionSequential(const Instr &InstrMeta) const; 111 bool isCFITrap(const Instr &InstrMeta) const; 117 bool canFallThrough(const Instr &InstrMeta) const; 126 const Instr *getDefiniteNextInstruction(const Instr &InstrMeta) const; 131 std::set<const Instr *> 132 getDirectControlFlowXRefs(const Instr &InstrMeta) const; [all …]
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D | FileAnalysis.cpp | 39 using Instr = llvm::cfi_verify::FileAnalysis::Instr; typedef 118 const Instr * 119 FileAnalysis::getPrevInstructionSequential(const Instr &InstrMeta) const { in getPrevInstructionSequential() 120 std::map<uint64_t, Instr>::const_iterator KV = in getPrevInstructionSequential() 131 const Instr * 132 FileAnalysis::getNextInstructionSequential(const Instr &InstrMeta) const { in getNextInstructionSequential() 133 std::map<uint64_t, Instr>::const_iterator KV = in getNextInstructionSequential() 144 bool FileAnalysis::usesRegisterOperand(const Instr &InstrMeta) const { in usesRegisterOperand() 152 const Instr *FileAnalysis::getInstruction(uint64_t Address) const { in getInstruction() 160 const Instr &FileAnalysis::getInstructionOrDie(uint64_t Address) const { in getInstructionOrDie() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/ |
D | Uops.cpp | 104 static bool hasTiedOperands(const Instruction &Instr, const Variable &Var) { in hasTiedOperands() argument 108 const Operand &Op = Instr.Operands[OpIndex]; in hasTiedOperands() 118 getTiedVariables(const Instruction &Instr) { in getTiedVariables() argument 120 for (const auto &Var : Instr.Variables) in getTiedVariables() 121 if (hasTiedOperands(Instr, Var)) in getTiedVariables() 139 const Instruction Instr(InstrDesc, RATC); in generatePrototype() local 140 const AliasingConfigurations SelfAliasing(Instr, Instr); in generatePrototype() 142 return generateUnconstrainedPrototype(Instr, "instruction is parallel"); in generatePrototype() 145 return generateUnconstrainedPrototype(Instr, "instruction is serial"); in generatePrototype() 147 const auto TiedVariables = getTiedVariables(Instr); in generatePrototype() [all …]
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D | MCInstrDescView.cpp | 86 InstructionInstance::InstructionInstance(const Instruction &Instr) in InstructionInstance() argument 87 : Instr(Instr), VariableValues(Instr.Variables.size()) {} in InstructionInstance() 95 return Instr.Description->getOpcode(); in getOpcode() 109 return getValueFor(Instr.Variables[Op.VariableIndex]); in getValueFor() 115 return getValueFor(Instr.Variables[Op.VariableIndex]); in getValueFor() 119 static void randomize(const Instruction &Instr, const Variable &Var, 123 return llvm::any_of(Instr.Variables, [this](const Variable &Var) { in hasImmediateVariables() 126 const Operand &Op = Instr.Operands[OpIndex]; in hasImmediateVariables() 133 for (const Variable &Var : Instr.Variables) { in randomizeUnsetVariables() 136 randomize(Instr, Var, AssignedValue); in randomizeUnsetVariables() [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMFeatures.h | 22 bool IsCPSRDead(InstrType *Instr); 25 inline bool isV8EligibleForIT(InstrType *Instr) { in isV8EligibleForIT() argument 26 switch (Instr->getOpcode()) { in isV8EligibleForIT() 53 return IsCPSRDead(Instr); in isV8EligibleForIT() 79 return Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT() 84 return Instr->getOperand(0).getReg() != ARM::PC; in isV8EligibleForIT() 86 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT() 87 Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT() 90 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT() 91 Instr->getOperand(1).getReg() != ARM::PC; in isV8EligibleForIT()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMFeatures.h | 22 bool IsCPSRDead(const InstrType *Instr); 25 inline bool isV8EligibleForIT(const InstrType *Instr) { in isV8EligibleForIT() argument 26 switch (Instr->getOpcode()) { in isV8EligibleForIT() 53 return IsCPSRDead(Instr); in isV8EligibleForIT() 79 return Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT() 84 return Instr->getOperand(0).getReg() != ARM::PC; in isV8EligibleForIT() 86 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT() 87 Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT() 90 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT() 91 Instr->getOperand(1).getReg() != ARM::PC; in isV8EligibleForIT()
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/external/llvm/lib/Target/AMDGPU/ |
D | R600OptimizeVectorRegisters.cpp | 65 MachineInstr *Instr; member in __anonc30efe020111::RegSeqInfo 68 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { in RegSeqInfo() 70 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) { in RegSeqInfo() 71 MachineOperand &MO = Instr->getOperand(i); in RegSeqInfo() 72 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo() 82 return RSI.Instr == Instr; in operator ==() 182 unsigned Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector() 183 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector() 187 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() 225 RSI->Instr->eraseFromParent(); in RebuildVector() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | R600OptimizeVectorRegisters.cpp | 77 MachineInstr *Instr; member in __anon22645c5a0111::RegSeqInfo 81 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { in RegSeqInfo() 83 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) { in RegSeqInfo() 84 MachineOperand &MO = Instr->getOperand(i); in RegSeqInfo() 85 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo() 96 return RSI.Instr == Instr; in operator ==() 206 unsigned Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector() 207 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector() 211 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() 247 RSI->Instr->eraseFromParent(); in RebuildVector() [all …]
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/external/v8/src/arm64/ |
D | assembler-arm64-inl.h | 881 Instr Assembler::Flags(FlagsUpdate S) { 891 Instr Assembler::Cond(Condition cond) { 896 Instr Assembler::ImmPCRelAddress(int imm21) { 898 Instr imm = static_cast<Instr>(truncate_to_int21(imm21)); 899 Instr immhi = (imm >> ImmPCRelLo_width) << ImmPCRelHi_offset; 900 Instr immlo = imm << ImmPCRelLo_offset; 905 Instr Assembler::ImmUncondBranch(int imm26) { 911 Instr Assembler::ImmCondBranch(int imm19) { 917 Instr Assembler::ImmCmpBranch(int imm19) { 923 Instr Assembler::ImmTestBranch(int imm14) { [all …]
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/external/llvm/lib/Target/Lanai/Disassembler/ |
D | LanaiDisassembler.cpp | 89 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument 93 if (isRMOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust() 95 else if (isSPLSOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust() 97 else if (isRRMOpcode(Instr.getOpcode())) { in PostOperandDecodeAdjust() 111 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust() 112 Instr.getOperand(2).setReg(Lanai::R0); in PostOperandDecodeAdjust() 114 if (Instr.getOperand(2).isImm()) in PostOperandDecodeAdjust() 115 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust() 126 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust() 130 DecodeStatus LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/Disassembler/ |
D | LanaiDisassembler.cpp | 89 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument 93 if (isRMOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust() 95 else if (isSPLSOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust() 97 else if (isRRMOpcode(Instr.getOpcode())) { in PostOperandDecodeAdjust() 111 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust() 112 Instr.getOperand(2).setReg(Lanai::R0); in PostOperandDecodeAdjust() 114 if (Instr.getOperand(2).isImm()) in PostOperandDecodeAdjust() 115 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust() 126 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust() 131 MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, in getInstruction() argument [all …]
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/external/v8/src/mips/ |
D | assembler-mips.cc | 285 const Instr kPopInstruction = ADDIU | (sp.code() << kRsShift) | 289 const Instr kPushInstruction = ADDIU | (sp.code() << kRsShift) | 293 const Instr kPushRegPattern = 296 const Instr kPopRegPattern = 299 const Instr kLwRegFpOffsetPattern = 302 const Instr kSwRegFpOffsetPattern = 305 const Instr kLwRegFpNegOffsetPattern = 308 const Instr kSwRegFpNegOffsetPattern = 311 const Instr kRtMask = kRtFieldMask; 312 const Instr kLwSwInstrTypeMask = 0xFFE00000; [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/Disassembler/ |
D | BPFDisassembler.cpp | 70 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 164 DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument 181 Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address, in getInstruction() 184 Result = decodeInstruction(DecoderTableBPF64, Instr, Insn, Address, this, in getInstruction() 189 switch (Instr.getOpcode()) { in getInstruction() 201 auto& Op = Instr.getOperand(1); in getInstruction() 211 auto Op = Instr.getOperand(0); in getInstruction() 212 Instr.clear(); in getInstruction() 213 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction() 214 Instr.addOperand(Op); in getInstruction()
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