| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.h | 50 bool IsRead; member
59 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false), in CodeGenSchedRW()
64 IsRead = Def->isSubClassOf("SchedRead"); in CodeGenSchedRW()
77 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false), in CodeGenSchedRW()
330 const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const { in getSchedRW() argument
331 return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx); in getSchedRW()
334 bool IsRead = Def->isSubClassOf("SchedRead"); in getSchedRW() local
335 unsigned Idx = getSchedRWIdx(Def, IsRead); in getSchedRW()
337 IsRead ? getSchedRead(Idx) : getSchedWrite(Idx)); in getSchedRW()
343 unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const;
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| D | CodeGenSchedule.cpp | 329 std::string CodeGenSchedModels::genRWName(ArrayRef<unsigned> Seq, bool IsRead) { in genRWName() argument
334 Name += getSchedRW(*I, IsRead).Name; in genRWName()
340 unsigned CodeGenSchedModels::getSchedRWIdx(Record *Def, bool IsRead, in getSchedRWIdx() argument
342 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in getSchedRWIdx()
393 bool IsRead) const { in findRWs()
395 unsigned Idx = getSchedRWIdx(*RI, IsRead); in findRWs()
402 bool IsRead) const { in expandRWSequence()
403 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead); in expandRWSequence()
413 expandRWSequence(*I, RWSeq, IsRead); in expandRWSequence()
421 unsigned RWIdx, IdxVec &RWSeq, bool IsRead, in expandRWSeqForProc() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenSchedule.h | 48 bool IsRead; member
57 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false), in CodeGenSchedRW()
62 IsRead = Def->isSubClassOf("SchedRead"); in CodeGenSchedRW()
75 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false), in CodeGenSchedRW()
378 const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const { in getSchedRW() argument
379 return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx); in getSchedRW()
382 bool IsRead = Def->isSubClassOf("SchedRead"); in getSchedRW() local
383 unsigned Idx = getSchedRWIdx(Def, IsRead); in getSchedRW()
385 IsRead ? getSchedRead(Idx) : getSchedWrite(Idx)); in getSchedRW()
391 unsigned getSchedRWIdx(const Record *Def, bool IsRead) const;
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| D | CodeGenSchedule.cpp | 447 std::string CodeGenSchedModels::genRWName(ArrayRef<unsigned> Seq, bool IsRead) { in genRWName() argument
452 Name += getSchedRW(*I, IsRead).Name; in genRWName()
459 bool IsRead) const { in getSchedRWIdx()
460 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in getSchedRWIdx()
504 bool IsRead) const { in findRWs()
506 unsigned Idx = getSchedRWIdx(RWDef, IsRead); in findRWs()
513 bool IsRead) const { in expandRWSequence()
514 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead); in expandRWSequence()
523 expandRWSequence(I, RWSeq, IsRead); in expandRWSequence()
531 unsigned RWIdx, IdxVec &RWSeq, bool IsRead, in expandRWSeqForProc() argument
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| /external/clang/include/clang/Sema/ |
| D | ScopeInfo.h | 284 WeakUseTy(const Expr *Use, bool IsRead) : Rep(Use, IsRead) {} in WeakUseTy() argument
321 inline void recordUseOfWeak(const ExprT *E, bool IsRead = true);
870 void FunctionScopeInfo::recordUseOfWeak(const ExprT *E, bool IsRead) { in recordUseOfWeak() argument
873 Uses.push_back(WeakUseTy(E, IsRead)); in recordUseOfWeak()
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| D | Sema.h | 1204 void recordUseOfEvaluatedWeak(const ExprT *E, bool IsRead=true) {
1206 getCurFunction()->recordUseOfWeak(E, IsRead);
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| /external/llvm/lib/Transforms/IPO/ |
| D | FunctionAttrs.cpp | 369 bool IsRead = false; in determinePointerReadAttrs() local
416 IsRead = true; in determinePointerReadAttrs()
458 IsRead = true; in determinePointerReadAttrs()
471 IsRead = true; in determinePointerReadAttrs()
483 return IsRead ? Attribute::ReadOnly : Attribute::ReadNone; in determinePointerReadAttrs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/IPO/ |
| D | FunctionAttrs.cpp | 414 bool IsRead = false; in determinePointerReadAttrs() local
461 IsRead = true; in determinePointerReadAttrs()
503 IsRead = true; in determinePointerReadAttrs()
516 IsRead = true; in determinePointerReadAttrs()
528 return IsRead ? Attribute::ReadOnly : Attribute::ReadNone; in determinePointerReadAttrs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| D | CFLGraph.h | 234 void addDerefEdge(Value *From, Value *To, bool IsRead) { in addDerefEdge() argument
245 if (IsRead) { in addDerefEdge()
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| /external/compiler-rt/lib/tsan/rtl/ |
| D | tsan_rtl.h | 250 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } in IsWrite()
251 bool ALWAYS_INLINE IsRead() const { return x_ & kReadBit; } in IsRead() function
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| D | tsan_rtl.cc | 666 old.IsRead() <= cur.IsRead()) in ContainsSameAccessSlow()
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| /external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/ |
| D | TilingFunctions.h | 693 template<bool UseCachedOffsets, bool IsRead>
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| /external/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 3861 bool IsRead, in EmitSpecialRegisterBuiltin() argument
3886 if (IsRead) { in EmitSpecialRegisterBuiltin()
4241 bool IsRead = BuiltinID == ARM::BI__builtin_arm_rsr || in EmitARMBuiltinExpr() local
4262 return EmitSpecialRegisterBuiltin(*this, E, RegisterType, ValueType, IsRead); in EmitARMBuiltinExpr()
4997 bool IsRead = BuiltinID == AArch64::BI__builtin_arm_rsr || in EmitAArch64BuiltinExpr() local
5017 return EmitSpecialRegisterBuiltin(*this, E, RegisterType, ValueType, IsRead); in EmitAArch64BuiltinExpr()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 3838 static int getMClassRegisterMask(StringRef Reg, StringRef Flags, bool IsRead, in getMClassRegisterMask() argument
3866 if (IsRead) { in getMClassRegisterMask()
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