| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmInstrumentation.cpp | 211 bool IsWrite,
215 bool IsWrite,
222 void InstrumentMemOperand(X86Operand &Op, unsigned AccessSize, bool IsWrite,
280 X86Operand &Op, unsigned AccessSize, bool IsWrite, in InstrumentMemOperand() argument
287 InstrumentMemOperandSmall(Op, AccessSize, IsWrite, RegCtx, Ctx, Out); in InstrumentMemOperand()
289 InstrumentMemOperandLarge(Op, AccessSize, IsWrite, RegCtx, Ctx, Out); in InstrumentMemOperand()
412 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore(); in InstrumentMOV() local
425 InstrumentMemOperand(MemOp, AccessSize, IsWrite, RegCtx, Ctx, Out); in InstrumentMOV()
582 bool IsWrite,
587 bool IsWrite,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmInstrumentation.cpp | 222 bool IsWrite,
226 bool IsWrite,
233 void InstrumentMemOperand(X86Operand &Op, unsigned AccessSize, bool IsWrite,
293 X86Operand &Op, unsigned AccessSize, bool IsWrite, in InstrumentMemOperand() argument
300 InstrumentMemOperandSmall(Op, AccessSize, IsWrite, RegCtx, Ctx, Out); in InstrumentMemOperand()
302 InstrumentMemOperandLarge(Op, AccessSize, IsWrite, RegCtx, Ctx, Out); in InstrumentMemOperand()
425 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore(); in InstrumentMOV() local
438 InstrumentMemOperand(MemOp, AccessSize, IsWrite, RegCtx, Ctx, Out); in InstrumentMOV()
595 bool IsWrite,
600 bool IsWrite,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Instrumentation/ |
| D | HWAddressSanitizer.cpp | 157 void instrumentMemAccessInline(Value *PtrLong, bool IsWrite,
161 Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite,
315 bool *IsWrite, in isInterestingMemoryAccess() argument
330 *IsWrite = false; in isInterestingMemoryAccess()
336 *IsWrite = true; in isInterestingMemoryAccess()
342 *IsWrite = true; in isInterestingMemoryAccess()
348 *IsWrite = true; in isInterestingMemoryAccess()
416 void HWAddressSanitizer::instrumentMemAccessInline(Value *PtrLong, bool IsWrite, in instrumentMemAccessInline() argument
441 const int64_t AccessInfo = Recover * 0x20 + IsWrite * 0x10 + AccessSizeIndex; in instrumentMemAccessInline()
469 bool IsWrite = false; in instrumentMemAccess() local
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| D | AddressSanitizer.cpp | 642 Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite,
650 Value *Addr, uint32_t TypeSize, bool IsWrite,
654 uint32_t TypeSize, bool IsWrite,
660 bool IsWrite, size_t AccessSizeIndex,
1208 bool *IsWrite, in isInterestingMemoryAccess() argument
1223 *IsWrite = false; in isInterestingMemoryAccess()
1229 *IsWrite = true; in isInterestingMemoryAccess()
1235 *IsWrite = true; in isInterestingMemoryAccess()
1241 *IsWrite = true; in isInterestingMemoryAccess()
1255 *IsWrite = true; in isInterestingMemoryAccess()
[all …]
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| D | ThreadSanitizer.cpp | 490 bool IsWrite = isa<StoreInst>(*I); in instrumentLoadOrStore() local
491 Value *Addr = IsWrite in instrumentLoadOrStore()
504 if (IsWrite && isVtableAccess(I)) { in instrumentLoadOrStore()
522 if (!IsWrite && isVtableAccess(I)) { in instrumentLoadOrStore()
528 const unsigned Alignment = IsWrite in instrumentLoadOrStore()
535 OnAccessFunc = IsWrite ? TsanWrite[Idx] : TsanRead[Idx]; in instrumentLoadOrStore()
537 OnAccessFunc = IsWrite ? TsanUnalignedWrite[Idx] : TsanUnalignedRead[Idx]; in instrumentLoadOrStore()
539 if (IsWrite) NumInstrumentedWrites++; in instrumentLoadOrStore()
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| /external/llvm/lib/Transforms/Instrumentation/ |
| D | AddressSanitizer.cpp | 480 Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite,
486 Value *Addr, uint32_t TypeSize, bool IsWrite,
489 uint32_t TypeSize, bool IsWrite,
495 bool IsWrite, size_t AccessSizeIndex,
938 bool *IsWrite, in isInterestingMemoryAccess() argument
948 *IsWrite = false; in isInterestingMemoryAccess()
954 *IsWrite = true; in isInterestingMemoryAccess()
960 *IsWrite = true; in isInterestingMemoryAccess()
966 *IsWrite = true; in isInterestingMemoryAccess()
1031 bool IsWrite = false; in instrumentMop() local
[all …]
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| D | ThreadSanitizer.cpp | 461 bool IsWrite = isa<StoreInst>(*I); in instrumentLoadOrStore() local
462 Value *Addr = IsWrite in instrumentLoadOrStore()
468 if (IsWrite && isVtableAccess(I)) { in instrumentLoadOrStore()
486 if (!IsWrite && isVtableAccess(I)) { in instrumentLoadOrStore()
492 const unsigned Alignment = IsWrite in instrumentLoadOrStore()
499 OnAccessFunc = IsWrite ? TsanWrite[Idx] : TsanRead[Idx]; in instrumentLoadOrStore()
501 OnAccessFunc = IsWrite ? TsanUnalignedWrite[Idx] : TsanUnalignedRead[Idx]; in instrumentLoadOrStore()
503 if (IsWrite) NumInstrumentedWrites++; in instrumentLoadOrStore()
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| /external/compiler-rt/lib/esan/ |
| D | esan.cpp | 65 void processRangeAccess(uptr PC, uptr Addr, int Size, bool IsWrite) { in processRangeAccess() argument
67 IsWrite ? 'w' : 'r', Addr, Size); in processRangeAccess()
72 processRangeAccessWorkingSet(PC, Addr, Size, IsWrite); in processRangeAccess()
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| D | working_set.h | 28 bool IsWrite);
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| D | esan.h | 45 void processRangeAccess(uptr PC, uptr Addr, int Size, bool IsWrite);
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| D | working_set.cpp | 82 bool IsWrite) { in processRangeAccessWorkingSet() argument
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| /external/compiler-rt/lib/tsan/rtl/ |
| D | tsan_rtl.h | 200 DCHECK_EQ(kAccessIsWrite, IsWrite()); in SetWrite()
250 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } in IsWrite() function
279 DCHECK_EQ(v, (!IsWrite() && !kIsWrite) || (IsAtomic() && kIsAtomic)); in IsBothReadsOrAtomic()
287 (IsAtomic() == kIsAtomic && !IsWrite() <= !kIsWrite)); in IsRWNotWeaker()
295 (IsAtomic() == kIsAtomic && !IsWrite() >= !kIsWrite)); in IsRWWeakerOrEqual()
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| D | tsan_rtl_report.cc | 171 mop->write = s.IsWrite(); in AddMemoryAccess()
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| /external/llvm/lib/Analysis/ |
| D | LoopAccessAnalysis.cpp | 609 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); in canCheckPtrAtRT() local
610 MemAccessInfo Access(Ptr, IsWrite); in canCheckPtrAtRT()
612 if (IsWrite) in canCheckPtrAtRT()
634 RtCheck.insert(TheLoop, Ptr, IsWrite, DepId, ASId, StridesMap, PSE); in canCheckPtrAtRT()
749 bool IsWrite = AC.getInt(); in processMemAccesses() local
753 bool IsReadOnlyPtr = ReadOnlyPtr.count(Ptr) && !IsWrite; in processMemAccesses()
758 assert(((IsReadOnlyPtr && UseDeferred) || IsWrite || in processMemAccesses()
762 MemAccessInfo Access(Ptr, IsWrite); in processMemAccesses()
779 if ((IsWrite || IsReadOnlyPtr) && SetHasWrite) { in processMemAccesses()
784 if (IsWrite) in processMemAccesses()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| D | LoopAccessAnalysis.cpp | 688 bool IsWrite = Access.getInt(); in createCheckForAccess() local
689 RtCheck.insert(TheLoop, Ptr, IsWrite, DepId, ASId, StridesMap, PSE); in createCheckForAccess()
725 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); in canCheckPtrAtRT() local
726 MemAccessInfo Access(Ptr, IsWrite); in canCheckPtrAtRT()
728 if (IsWrite) in canCheckPtrAtRT()
867 bool IsWrite = AC.getInt(); in processMemAccesses() local
871 bool IsReadOnlyPtr = ReadOnlyPtr.count(Ptr) && !IsWrite; in processMemAccesses()
876 assert(((IsReadOnlyPtr && UseDeferred) || IsWrite || in processMemAccesses()
880 MemAccessInfo Access(Ptr, IsWrite); in processMemAccesses()
897 if ((IsWrite || IsReadOnlyPtr) && SetHasWrite) { in processMemAccesses()
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| /external/compiler-rt/lib/tsan/tests/unit/ |
| D | tsan_shadow_test.cc | 28 EXPECT_EQ(s.IsWrite(), true); in TEST()
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| /external/pdfium/third_party/lcms/src/ |
| D | cmsio0.c | 1074 NewIcc -> IsWrite = TRUE; in cmsOpenProfileFromIOhandler2THR()
1102 NewIcc -> IsWrite = TRUE; in cmsOpenProfileFromFileTHR()
1136 NewIcc -> IsWrite = TRUE; in cmsOpenProfileFromStreamTHR()
1461 if (Icc ->IsWrite) { in cmsCloseProfile()
1463 Icc ->IsWrite = FALSE; // Assure no further writting in cmsCloseProfile()
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| D | lcms2_internal.h | 751 cmsBool IsWrite; member
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 3402 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); in lowerPREFETCH() local
3403 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ; in lowerPREFETCH()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 3642 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); in lowerPREFETCH() local
3643 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ; in lowerPREFETCH()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1864 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); in LowerPREFETCH() local
1880 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit in LowerPREFETCH()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2188 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); in LowerPREFETCH() local
2204 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit in LowerPREFETCH()
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