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Searched refs:Itins (Results 1 – 7 of 7) sorted by relevance

/external/swiftshader/third_party/LLVM/utils/TableGen/
DSubtargetEmitter.cpp477 std::vector<Record*> Itins = in EmitProcessorData() local
479 for (unsigned i = 0, N = Itins.size(); i < N; i++) { in EmitProcessorData()
481 Record *Itin = Itins[i]; in EmitProcessorData()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.h375 const InstrItineraryData *Itins; variable
DARMISelLowering.cpp180 Itins = TM.getInstrItineraryData(); in ARMTargetLowering()
1000 if (!Itins->isEmpty() && in getSchedulingPreference()
1001 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) in getSchedulingPreference()
/external/llvm/lib/Target/ARM/
DARMISelLowering.h493 const InstrItineraryData *Itins; variable
DARMISelLowering.cpp166 Itins = Subtarget->getInstrItineraryData(); in ARMTargetLowering()
1317 if (!Itins->isEmpty() && in getSchedulingPreference()
1318 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) in getSchedulingPreference()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelLowering.h598 const InstrItineraryData *Itins; variable
DARMISelLowering.cpp227 Itins = Subtarget->getInstrItineraryData(); in ARMTargetLowering()
1460 if (!Itins->isEmpty() && in getSchedulingPreference()
1461 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) in getSchedulingPreference()