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Searched refs:JALR (Results 1 – 25 of 56) sorted by relevance

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/external/llvm/test/CodeGen/Mips/llvm-ir/
Dret.ll32 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
43 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
53 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
63 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
73 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
83 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
93 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
104 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
119 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
135 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
[all …]
Dindirectbr.ll23 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
24 ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
29 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
30 ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/
Dret.ll32 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
43 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
53 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
63 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
73 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
83 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
93 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
104 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
119 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
135 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
[all …]
Dindirectbr.ll23 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
24 ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
29 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
30 ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
Dstore.ll46 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
156 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
266 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
408 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
Dload.ll47 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
186 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
326 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
465 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
605 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
755 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
910 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
/external/llvm/test/CodeGen/Mips/
Dlongbranch.ll79 ; In MIPS32R6 JR is an alias to JALR with $rd=0. As everything else remains the
81 ; the opcode of the MachineInst is a JALR.
82 ; O32-R6: JALR
112 ; In MIPS64R6 JR is an alias to JALR with $rd=0. As everything else remains the
114 ; the opcode of the MachineInst is a JALR.
Deh-return32.ll47 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
87 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
Deh-return64.ll48 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
90 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp51 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump()
81 case Mips::JALR: in isCall()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp60 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump()
90 case Mips::JALR: in isCall()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Deh-return32.ll47 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
87 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
Deh-return64.ll48 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
90 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/MCTargetDesc/
DRISCVMCCodeEmitter.cpp120 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
123 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); in expandFunctionCall()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsEmitGPRestore.cpp73 if (I->getOpcode() != Mips::JALR) { in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td299 def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
521 def : InstAlias<"jr $rs", (JALR X0, GPR:$rs, 0)>;
522 def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0)>;
523 def : InstAlias<"ret", (JALR X0, X1, 0), 2>;
673 PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;
699 PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
703 PseudoInstExpansion<(JALR X0, X1, 0)>;
716 PseudoInstExpansion<(JALR X0, GPR:$rs1, 0)>;
DRISCVInstrInfoC.td672 def : CompressPat<(JALR X0, GPRNoX0:$rs1, 0),
681 def : CompressPat<(JALR X1, GPRNoX0:$rs1, 0),
/external/v8/src/mips/
Dconstants-mips.h509 JALR = ((1U << 3) + 1), enumerator
1281 FunctionFieldToBitNumber(JR) | FunctionFieldToBitNumber(JALR) |
1827 case JALR: in IsLinkingInstruction()
1893 case JALR: in IsForbiddenAfterBranchInstr()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenMCPseudoLowering.inc244 TmpInst.setOpcode(Mips::JALR);
280 TmpInst.setOpcode(Mips::JALR);
563 TmpInst.setOpcode(Mips::JALR);
826 TmpInst.setOpcode(Mips::JALR);
/external/v8/src/mips64/
Dconstants-mips64.h491 JALR = ((1U << 3) + 1), enumerator
1318 FunctionFieldToBitNumber(JR) | FunctionFieldToBitNumber(JALR) |
1910 case JALR: in IsLinkingInstruction()
1976 case JALR: in IsForbiddenAfterBranchInstr()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.cpp248 case Mips::JALR: in printAlias()
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.cpp253 case Mips::JALR: in printAlias()
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_32.c631 PTR_FAIL_IF(push_inst(compiler, JALR | S(PIC_ADDR_REG) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); in sljit_emit_call()
663 FAIL_IF(push_inst(compiler, JALR | S(PIC_ADDR_REG) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); in sljit_emit_icall()
DsljitNativeMIPS_64.c636 PTR_FAIL_IF(push_inst(compiler, JALR | S(PIC_ADDR_REG) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); in sljit_emit_call()
666 FAIL_IF(push_inst(compiler, JALR | S(PIC_ADDR_REG) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); in sljit_emit_icall()
/external/llvm/lib/Target/Mips/
DMipsLongBranch.cpp341 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR)) in expandToLongBranch()

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