1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Pseudo-instruction MC lowering Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9bool MipsAsmPrinter:: 10emitPseudoExpansionLowering(MCStreamer &OutStreamer, 11 const MachineInstr *MI) { 12 switch (MI->getOpcode()) { 13 default: return false; 14 case Mips::AND_V_D_PSEUDO: { 15 MCInst TmpInst; 16 MCOperand MCOp; 17 TmpInst.setOpcode(Mips::AND_V); 18 // Operand: wd 19 lowerOperand(MI->getOperand(0), MCOp); 20 TmpInst.addOperand(MCOp); 21 // Operand: ws 22 lowerOperand(MI->getOperand(1), MCOp); 23 TmpInst.addOperand(MCOp); 24 // Operand: wt 25 lowerOperand(MI->getOperand(2), MCOp); 26 TmpInst.addOperand(MCOp); 27 EmitToStreamer(OutStreamer, TmpInst); 28 break; 29 } 30 case Mips::AND_V_H_PSEUDO: { 31 MCInst TmpInst; 32 MCOperand MCOp; 33 TmpInst.setOpcode(Mips::AND_V); 34 // Operand: wd 35 lowerOperand(MI->getOperand(0), MCOp); 36 TmpInst.addOperand(MCOp); 37 // Operand: ws 38 lowerOperand(MI->getOperand(1), MCOp); 39 TmpInst.addOperand(MCOp); 40 // Operand: wt 41 lowerOperand(MI->getOperand(2), MCOp); 42 TmpInst.addOperand(MCOp); 43 EmitToStreamer(OutStreamer, TmpInst); 44 break; 45 } 46 case Mips::AND_V_W_PSEUDO: { 47 MCInst TmpInst; 48 MCOperand MCOp; 49 TmpInst.setOpcode(Mips::AND_V); 50 // Operand: wd 51 lowerOperand(MI->getOperand(0), MCOp); 52 TmpInst.addOperand(MCOp); 53 // Operand: ws 54 lowerOperand(MI->getOperand(1), MCOp); 55 TmpInst.addOperand(MCOp); 56 // Operand: wt 57 lowerOperand(MI->getOperand(2), MCOp); 58 TmpInst.addOperand(MCOp); 59 EmitToStreamer(OutStreamer, TmpInst); 60 break; 61 } 62 case Mips::B: { 63 MCInst TmpInst; 64 MCOperand MCOp; 65 TmpInst.setOpcode(Mips::BEQ); 66 // Operand: rs 67 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 68 // Operand: rt 69 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 70 // Operand: offset 71 lowerOperand(MI->getOperand(0), MCOp); 72 TmpInst.addOperand(MCOp); 73 EmitToStreamer(OutStreamer, TmpInst); 74 break; 75 } 76 case Mips::BAL_BR: { 77 MCInst TmpInst; 78 MCOperand MCOp; 79 TmpInst.setOpcode(Mips::BGEZAL); 80 // Operand: rs 81 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 82 // Operand: offset 83 lowerOperand(MI->getOperand(0), MCOp); 84 TmpInst.addOperand(MCOp); 85 EmitToStreamer(OutStreamer, TmpInst); 86 break; 87 } 88 case Mips::BAL_BR_MM: { 89 MCInst TmpInst; 90 MCOperand MCOp; 91 TmpInst.setOpcode(Mips::BGEZAL_MM); 92 // Operand: rs 93 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 94 // Operand: offset 95 lowerOperand(MI->getOperand(0), MCOp); 96 TmpInst.addOperand(MCOp); 97 EmitToStreamer(OutStreamer, TmpInst); 98 break; 99 } 100 case Mips::BSEL_D_PSEUDO: { 101 MCInst TmpInst; 102 MCOperand MCOp; 103 TmpInst.setOpcode(Mips::BSEL_V); 104 // Operand: wd 105 lowerOperand(MI->getOperand(0), MCOp); 106 TmpInst.addOperand(MCOp); 107 // Operand: wd_in 108 lowerOperand(MI->getOperand(1), MCOp); 109 TmpInst.addOperand(MCOp); 110 // Operand: ws 111 lowerOperand(MI->getOperand(2), MCOp); 112 TmpInst.addOperand(MCOp); 113 // Operand: wt 114 lowerOperand(MI->getOperand(3), MCOp); 115 TmpInst.addOperand(MCOp); 116 EmitToStreamer(OutStreamer, TmpInst); 117 break; 118 } 119 case Mips::BSEL_FD_PSEUDO: { 120 MCInst TmpInst; 121 MCOperand MCOp; 122 TmpInst.setOpcode(Mips::BSEL_V); 123 // Operand: wd 124 lowerOperand(MI->getOperand(0), MCOp); 125 TmpInst.addOperand(MCOp); 126 // Operand: wd_in 127 lowerOperand(MI->getOperand(1), MCOp); 128 TmpInst.addOperand(MCOp); 129 // Operand: ws 130 lowerOperand(MI->getOperand(2), MCOp); 131 TmpInst.addOperand(MCOp); 132 // Operand: wt 133 lowerOperand(MI->getOperand(3), MCOp); 134 TmpInst.addOperand(MCOp); 135 EmitToStreamer(OutStreamer, TmpInst); 136 break; 137 } 138 case Mips::BSEL_FW_PSEUDO: { 139 MCInst TmpInst; 140 MCOperand MCOp; 141 TmpInst.setOpcode(Mips::BSEL_V); 142 // Operand: wd 143 lowerOperand(MI->getOperand(0), MCOp); 144 TmpInst.addOperand(MCOp); 145 // Operand: wd_in 146 lowerOperand(MI->getOperand(1), MCOp); 147 TmpInst.addOperand(MCOp); 148 // Operand: ws 149 lowerOperand(MI->getOperand(2), MCOp); 150 TmpInst.addOperand(MCOp); 151 // Operand: wt 152 lowerOperand(MI->getOperand(3), MCOp); 153 TmpInst.addOperand(MCOp); 154 EmitToStreamer(OutStreamer, TmpInst); 155 break; 156 } 157 case Mips::BSEL_H_PSEUDO: { 158 MCInst TmpInst; 159 MCOperand MCOp; 160 TmpInst.setOpcode(Mips::BSEL_V); 161 // Operand: wd 162 lowerOperand(MI->getOperand(0), MCOp); 163 TmpInst.addOperand(MCOp); 164 // Operand: wd_in 165 lowerOperand(MI->getOperand(1), MCOp); 166 TmpInst.addOperand(MCOp); 167 // Operand: ws 168 lowerOperand(MI->getOperand(2), MCOp); 169 TmpInst.addOperand(MCOp); 170 // Operand: wt 171 lowerOperand(MI->getOperand(3), MCOp); 172 TmpInst.addOperand(MCOp); 173 EmitToStreamer(OutStreamer, TmpInst); 174 break; 175 } 176 case Mips::BSEL_W_PSEUDO: { 177 MCInst TmpInst; 178 MCOperand MCOp; 179 TmpInst.setOpcode(Mips::BSEL_V); 180 // Operand: wd 181 lowerOperand(MI->getOperand(0), MCOp); 182 TmpInst.addOperand(MCOp); 183 // Operand: wd_in 184 lowerOperand(MI->getOperand(1), MCOp); 185 TmpInst.addOperand(MCOp); 186 // Operand: ws 187 lowerOperand(MI->getOperand(2), MCOp); 188 TmpInst.addOperand(MCOp); 189 // Operand: wt 190 lowerOperand(MI->getOperand(3), MCOp); 191 TmpInst.addOperand(MCOp); 192 EmitToStreamer(OutStreamer, TmpInst); 193 break; 194 } 195 case Mips::B_MM: { 196 MCInst TmpInst; 197 MCOperand MCOp; 198 TmpInst.setOpcode(Mips::BEQ_MM); 199 // Operand: rs 200 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 201 // Operand: rt 202 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 203 // Operand: offset 204 lowerOperand(MI->getOperand(0), MCOp); 205 TmpInst.addOperand(MCOp); 206 EmitToStreamer(OutStreamer, TmpInst); 207 break; 208 } 209 case Mips::FABS_D: { 210 MCInst TmpInst; 211 MCOperand MCOp; 212 TmpInst.setOpcode(Mips::FMAX_A_D); 213 // Operand: wd 214 lowerOperand(MI->getOperand(0), MCOp); 215 TmpInst.addOperand(MCOp); 216 // Operand: ws 217 lowerOperand(MI->getOperand(1), MCOp); 218 TmpInst.addOperand(MCOp); 219 // Operand: wt 220 lowerOperand(MI->getOperand(1), MCOp); 221 TmpInst.addOperand(MCOp); 222 EmitToStreamer(OutStreamer, TmpInst); 223 break; 224 } 225 case Mips::FABS_W: { 226 MCInst TmpInst; 227 MCOperand MCOp; 228 TmpInst.setOpcode(Mips::FMAX_A_W); 229 // Operand: wd 230 lowerOperand(MI->getOperand(0), MCOp); 231 TmpInst.addOperand(MCOp); 232 // Operand: ws 233 lowerOperand(MI->getOperand(1), MCOp); 234 TmpInst.addOperand(MCOp); 235 // Operand: wt 236 lowerOperand(MI->getOperand(1), MCOp); 237 TmpInst.addOperand(MCOp); 238 EmitToStreamer(OutStreamer, TmpInst); 239 break; 240 } 241 case Mips::JALR64Pseudo: { 242 MCInst TmpInst; 243 MCOperand MCOp; 244 TmpInst.setOpcode(Mips::JALR); 245 // Operand: rd 246 TmpInst.addOperand(MCOperand::createReg(Mips::RA)); 247 // Operand: rs 248 lowerOperand(MI->getOperand(0), MCOp); 249 TmpInst.addOperand(MCOp); 250 EmitToStreamer(OutStreamer, TmpInst); 251 break; 252 } 253 case Mips::JALRHB64Pseudo: { 254 MCInst TmpInst; 255 MCOperand MCOp; 256 TmpInst.setOpcode(Mips::JALR_HB64); 257 // Operand: rd 258 TmpInst.addOperand(MCOperand::createReg(Mips::RA_64)); 259 // Operand: rs 260 lowerOperand(MI->getOperand(0), MCOp); 261 TmpInst.addOperand(MCOp); 262 EmitToStreamer(OutStreamer, TmpInst); 263 break; 264 } 265 case Mips::JALRHBPseudo: { 266 MCInst TmpInst; 267 MCOperand MCOp; 268 TmpInst.setOpcode(Mips::JALR_HB); 269 // Operand: rd 270 TmpInst.addOperand(MCOperand::createReg(Mips::RA)); 271 // Operand: rs 272 lowerOperand(MI->getOperand(0), MCOp); 273 TmpInst.addOperand(MCOp); 274 EmitToStreamer(OutStreamer, TmpInst); 275 break; 276 } 277 case Mips::JALRPseudo: { 278 MCInst TmpInst; 279 MCOperand MCOp; 280 TmpInst.setOpcode(Mips::JALR); 281 // Operand: rd 282 TmpInst.addOperand(MCOperand::createReg(Mips::RA)); 283 // Operand: rs 284 lowerOperand(MI->getOperand(0), MCOp); 285 TmpInst.addOperand(MCOp); 286 EmitToStreamer(OutStreamer, TmpInst); 287 break; 288 } 289 case Mips::NOP: { 290 MCInst TmpInst; 291 MCOperand MCOp; 292 TmpInst.setOpcode(Mips::SLL); 293 // Operand: rd 294 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 295 // Operand: rt 296 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 297 // Operand: shamt 298 TmpInst.addOperand(MCOperand::createImm(0)); 299 EmitToStreamer(OutStreamer, TmpInst); 300 break; 301 } 302 case Mips::NOR_V_D_PSEUDO: { 303 MCInst TmpInst; 304 MCOperand MCOp; 305 TmpInst.setOpcode(Mips::NOR_V); 306 // Operand: wd 307 lowerOperand(MI->getOperand(0), MCOp); 308 TmpInst.addOperand(MCOp); 309 // Operand: ws 310 lowerOperand(MI->getOperand(1), MCOp); 311 TmpInst.addOperand(MCOp); 312 // Operand: wt 313 lowerOperand(MI->getOperand(2), MCOp); 314 TmpInst.addOperand(MCOp); 315 EmitToStreamer(OutStreamer, TmpInst); 316 break; 317 } 318 case Mips::NOR_V_H_PSEUDO: { 319 MCInst TmpInst; 320 MCOperand MCOp; 321 TmpInst.setOpcode(Mips::NOR_V); 322 // Operand: wd 323 lowerOperand(MI->getOperand(0), MCOp); 324 TmpInst.addOperand(MCOp); 325 // Operand: ws 326 lowerOperand(MI->getOperand(1), MCOp); 327 TmpInst.addOperand(MCOp); 328 // Operand: wt 329 lowerOperand(MI->getOperand(2), MCOp); 330 TmpInst.addOperand(MCOp); 331 EmitToStreamer(OutStreamer, TmpInst); 332 break; 333 } 334 case Mips::NOR_V_W_PSEUDO: { 335 MCInst TmpInst; 336 MCOperand MCOp; 337 TmpInst.setOpcode(Mips::NOR_V); 338 // Operand: wd 339 lowerOperand(MI->getOperand(0), MCOp); 340 TmpInst.addOperand(MCOp); 341 // Operand: ws 342 lowerOperand(MI->getOperand(1), MCOp); 343 TmpInst.addOperand(MCOp); 344 // Operand: wt 345 lowerOperand(MI->getOperand(2), MCOp); 346 TmpInst.addOperand(MCOp); 347 EmitToStreamer(OutStreamer, TmpInst); 348 break; 349 } 350 case Mips::OR_V_D_PSEUDO: { 351 MCInst TmpInst; 352 MCOperand MCOp; 353 TmpInst.setOpcode(Mips::OR_V); 354 // Operand: wd 355 lowerOperand(MI->getOperand(0), MCOp); 356 TmpInst.addOperand(MCOp); 357 // Operand: ws 358 lowerOperand(MI->getOperand(1), MCOp); 359 TmpInst.addOperand(MCOp); 360 // Operand: wt 361 lowerOperand(MI->getOperand(2), MCOp); 362 TmpInst.addOperand(MCOp); 363 EmitToStreamer(OutStreamer, TmpInst); 364 break; 365 } 366 case Mips::OR_V_H_PSEUDO: { 367 MCInst TmpInst; 368 MCOperand MCOp; 369 TmpInst.setOpcode(Mips::OR_V); 370 // Operand: wd 371 lowerOperand(MI->getOperand(0), MCOp); 372 TmpInst.addOperand(MCOp); 373 // Operand: ws 374 lowerOperand(MI->getOperand(1), MCOp); 375 TmpInst.addOperand(MCOp); 376 // Operand: wt 377 lowerOperand(MI->getOperand(2), MCOp); 378 TmpInst.addOperand(MCOp); 379 EmitToStreamer(OutStreamer, TmpInst); 380 break; 381 } 382 case Mips::OR_V_W_PSEUDO: { 383 MCInst TmpInst; 384 MCOperand MCOp; 385 TmpInst.setOpcode(Mips::OR_V); 386 // Operand: wd 387 lowerOperand(MI->getOperand(0), MCOp); 388 TmpInst.addOperand(MCOp); 389 // Operand: ws 390 lowerOperand(MI->getOperand(1), MCOp); 391 TmpInst.addOperand(MCOp); 392 // Operand: wt 393 lowerOperand(MI->getOperand(2), MCOp); 394 TmpInst.addOperand(MCOp); 395 EmitToStreamer(OutStreamer, TmpInst); 396 break; 397 } 398 case Mips::PseudoCMPU_EQ_QB: { 399 MCInst TmpInst; 400 MCOperand MCOp; 401 TmpInst.setOpcode(Mips::CMPU_EQ_QB); 402 // Operand: rs 403 lowerOperand(MI->getOperand(1), MCOp); 404 TmpInst.addOperand(MCOp); 405 // Operand: rt 406 lowerOperand(MI->getOperand(2), MCOp); 407 TmpInst.addOperand(MCOp); 408 EmitToStreamer(OutStreamer, TmpInst); 409 break; 410 } 411 case Mips::PseudoCMPU_LE_QB: { 412 MCInst TmpInst; 413 MCOperand MCOp; 414 TmpInst.setOpcode(Mips::CMPU_LE_QB); 415 // Operand: rs 416 lowerOperand(MI->getOperand(1), MCOp); 417 TmpInst.addOperand(MCOp); 418 // Operand: rt 419 lowerOperand(MI->getOperand(2), MCOp); 420 TmpInst.addOperand(MCOp); 421 EmitToStreamer(OutStreamer, TmpInst); 422 break; 423 } 424 case Mips::PseudoCMPU_LT_QB: { 425 MCInst TmpInst; 426 MCOperand MCOp; 427 TmpInst.setOpcode(Mips::CMPU_LT_QB); 428 // Operand: rs 429 lowerOperand(MI->getOperand(1), MCOp); 430 TmpInst.addOperand(MCOp); 431 // Operand: rt 432 lowerOperand(MI->getOperand(2), MCOp); 433 TmpInst.addOperand(MCOp); 434 EmitToStreamer(OutStreamer, TmpInst); 435 break; 436 } 437 case Mips::PseudoCMP_EQ_PH: { 438 MCInst TmpInst; 439 MCOperand MCOp; 440 TmpInst.setOpcode(Mips::CMP_EQ_PH); 441 // Operand: rs 442 lowerOperand(MI->getOperand(1), MCOp); 443 TmpInst.addOperand(MCOp); 444 // Operand: rt 445 lowerOperand(MI->getOperand(2), MCOp); 446 TmpInst.addOperand(MCOp); 447 EmitToStreamer(OutStreamer, TmpInst); 448 break; 449 } 450 case Mips::PseudoCMP_LE_PH: { 451 MCInst TmpInst; 452 MCOperand MCOp; 453 TmpInst.setOpcode(Mips::CMP_LE_PH); 454 // Operand: rs 455 lowerOperand(MI->getOperand(1), MCOp); 456 TmpInst.addOperand(MCOp); 457 // Operand: rt 458 lowerOperand(MI->getOperand(2), MCOp); 459 TmpInst.addOperand(MCOp); 460 EmitToStreamer(OutStreamer, TmpInst); 461 break; 462 } 463 case Mips::PseudoCMP_LT_PH: { 464 MCInst TmpInst; 465 MCOperand MCOp; 466 TmpInst.setOpcode(Mips::CMP_LT_PH); 467 // Operand: rs 468 lowerOperand(MI->getOperand(1), MCOp); 469 TmpInst.addOperand(MCOp); 470 // Operand: rt 471 lowerOperand(MI->getOperand(2), MCOp); 472 TmpInst.addOperand(MCOp); 473 EmitToStreamer(OutStreamer, TmpInst); 474 break; 475 } 476 case Mips::PseudoDMULT: { 477 MCInst TmpInst; 478 MCOperand MCOp; 479 TmpInst.setOpcode(Mips::DMULT); 480 // Operand: rs 481 lowerOperand(MI->getOperand(1), MCOp); 482 TmpInst.addOperand(MCOp); 483 // Operand: rt 484 lowerOperand(MI->getOperand(2), MCOp); 485 TmpInst.addOperand(MCOp); 486 EmitToStreamer(OutStreamer, TmpInst); 487 break; 488 } 489 case Mips::PseudoDMULTu: { 490 MCInst TmpInst; 491 MCOperand MCOp; 492 TmpInst.setOpcode(Mips::DMULTu); 493 // Operand: rs 494 lowerOperand(MI->getOperand(1), MCOp); 495 TmpInst.addOperand(MCOp); 496 // Operand: rt 497 lowerOperand(MI->getOperand(2), MCOp); 498 TmpInst.addOperand(MCOp); 499 EmitToStreamer(OutStreamer, TmpInst); 500 break; 501 } 502 case Mips::PseudoDSDIV: { 503 MCInst TmpInst; 504 MCOperand MCOp; 505 TmpInst.setOpcode(Mips::DSDIV); 506 // Operand: rs 507 lowerOperand(MI->getOperand(1), MCOp); 508 TmpInst.addOperand(MCOp); 509 // Operand: rt 510 lowerOperand(MI->getOperand(2), MCOp); 511 TmpInst.addOperand(MCOp); 512 EmitToStreamer(OutStreamer, TmpInst); 513 break; 514 } 515 case Mips::PseudoDUDIV: { 516 MCInst TmpInst; 517 MCOperand MCOp; 518 TmpInst.setOpcode(Mips::DUDIV); 519 // Operand: rs 520 lowerOperand(MI->getOperand(1), MCOp); 521 TmpInst.addOperand(MCOp); 522 // Operand: rt 523 lowerOperand(MI->getOperand(2), MCOp); 524 TmpInst.addOperand(MCOp); 525 EmitToStreamer(OutStreamer, TmpInst); 526 break; 527 } 528 case Mips::PseudoIndirectBranch: { 529 MCInst TmpInst; 530 MCOperand MCOp; 531 TmpInst.setOpcode(Mips::JR); 532 // Operand: rs 533 lowerOperand(MI->getOperand(0), MCOp); 534 TmpInst.addOperand(MCOp); 535 EmitToStreamer(OutStreamer, TmpInst); 536 break; 537 } 538 case Mips::PseudoIndirectBranch64: { 539 MCInst TmpInst; 540 MCOperand MCOp; 541 TmpInst.setOpcode(Mips::JR64); 542 // Operand: rs 543 lowerOperand(MI->getOperand(0), MCOp); 544 TmpInst.addOperand(MCOp); 545 EmitToStreamer(OutStreamer, TmpInst); 546 break; 547 } 548 case Mips::PseudoIndirectBranch64R6: { 549 MCInst TmpInst; 550 MCOperand MCOp; 551 TmpInst.setOpcode(Mips::JALR64); 552 // Operand: rd 553 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO_64)); 554 // Operand: rs 555 lowerOperand(MI->getOperand(0), MCOp); 556 TmpInst.addOperand(MCOp); 557 EmitToStreamer(OutStreamer, TmpInst); 558 break; 559 } 560 case Mips::PseudoIndirectBranchR6: { 561 MCInst TmpInst; 562 MCOperand MCOp; 563 TmpInst.setOpcode(Mips::JALR); 564 // Operand: rd 565 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 566 // Operand: rs 567 lowerOperand(MI->getOperand(0), MCOp); 568 TmpInst.addOperand(MCOp); 569 EmitToStreamer(OutStreamer, TmpInst); 570 break; 571 } 572 case Mips::PseudoIndirectBranch_MM: { 573 MCInst TmpInst; 574 MCOperand MCOp; 575 TmpInst.setOpcode(Mips::JR_MM); 576 // Operand: rs 577 lowerOperand(MI->getOperand(0), MCOp); 578 TmpInst.addOperand(MCOp); 579 EmitToStreamer(OutStreamer, TmpInst); 580 break; 581 } 582 case Mips::PseudoIndirectBranch_MMR6: { 583 MCInst TmpInst; 584 MCOperand MCOp; 585 TmpInst.setOpcode(Mips::JRC16_MMR6); 586 // Operand: rs 587 lowerOperand(MI->getOperand(0), MCOp); 588 TmpInst.addOperand(MCOp); 589 EmitToStreamer(OutStreamer, TmpInst); 590 break; 591 } 592 case Mips::PseudoIndirectHazardBranch: { 593 MCInst TmpInst; 594 MCOperand MCOp; 595 TmpInst.setOpcode(Mips::JR_HB); 596 // Operand: rs 597 lowerOperand(MI->getOperand(0), MCOp); 598 TmpInst.addOperand(MCOp); 599 EmitToStreamer(OutStreamer, TmpInst); 600 break; 601 } 602 case Mips::PseudoIndirectHazardBranch64: { 603 MCInst TmpInst; 604 MCOperand MCOp; 605 TmpInst.setOpcode(Mips::JR_HB64); 606 // Operand: rs 607 lowerOperand(MI->getOperand(0), MCOp); 608 TmpInst.addOperand(MCOp); 609 EmitToStreamer(OutStreamer, TmpInst); 610 break; 611 } 612 case Mips::PseudoIndrectHazardBranch64R6: { 613 MCInst TmpInst; 614 MCOperand MCOp; 615 TmpInst.setOpcode(Mips::JR_HB64_R6); 616 // Operand: rs 617 lowerOperand(MI->getOperand(0), MCOp); 618 TmpInst.addOperand(MCOp); 619 EmitToStreamer(OutStreamer, TmpInst); 620 break; 621 } 622 case Mips::PseudoIndrectHazardBranchR6: { 623 MCInst TmpInst; 624 MCOperand MCOp; 625 TmpInst.setOpcode(Mips::JR_HB_R6); 626 // Operand: rs 627 lowerOperand(MI->getOperand(0), MCOp); 628 TmpInst.addOperand(MCOp); 629 EmitToStreamer(OutStreamer, TmpInst); 630 break; 631 } 632 case Mips::PseudoMADD: { 633 MCInst TmpInst; 634 MCOperand MCOp; 635 TmpInst.setOpcode(Mips::MADD); 636 // Operand: rs 637 lowerOperand(MI->getOperand(1), MCOp); 638 TmpInst.addOperand(MCOp); 639 // Operand: rt 640 lowerOperand(MI->getOperand(2), MCOp); 641 TmpInst.addOperand(MCOp); 642 EmitToStreamer(OutStreamer, TmpInst); 643 break; 644 } 645 case Mips::PseudoMADDU: { 646 MCInst TmpInst; 647 MCOperand MCOp; 648 TmpInst.setOpcode(Mips::MADDU); 649 // Operand: rs 650 lowerOperand(MI->getOperand(1), MCOp); 651 TmpInst.addOperand(MCOp); 652 // Operand: rt 653 lowerOperand(MI->getOperand(2), MCOp); 654 TmpInst.addOperand(MCOp); 655 EmitToStreamer(OutStreamer, TmpInst); 656 break; 657 } 658 case Mips::PseudoMSUB: { 659 MCInst TmpInst; 660 MCOperand MCOp; 661 TmpInst.setOpcode(Mips::MSUB); 662 // Operand: rs 663 lowerOperand(MI->getOperand(1), MCOp); 664 TmpInst.addOperand(MCOp); 665 // Operand: rt 666 lowerOperand(MI->getOperand(2), MCOp); 667 TmpInst.addOperand(MCOp); 668 EmitToStreamer(OutStreamer, TmpInst); 669 break; 670 } 671 case Mips::PseudoMSUBU: { 672 MCInst TmpInst; 673 MCOperand MCOp; 674 TmpInst.setOpcode(Mips::MSUBU); 675 // Operand: rs 676 lowerOperand(MI->getOperand(1), MCOp); 677 TmpInst.addOperand(MCOp); 678 // Operand: rt 679 lowerOperand(MI->getOperand(2), MCOp); 680 TmpInst.addOperand(MCOp); 681 EmitToStreamer(OutStreamer, TmpInst); 682 break; 683 } 684 case Mips::PseudoMULT: { 685 MCInst TmpInst; 686 MCOperand MCOp; 687 TmpInst.setOpcode(Mips::MULT); 688 // Operand: rs 689 lowerOperand(MI->getOperand(1), MCOp); 690 TmpInst.addOperand(MCOp); 691 // Operand: rt 692 lowerOperand(MI->getOperand(2), MCOp); 693 TmpInst.addOperand(MCOp); 694 EmitToStreamer(OutStreamer, TmpInst); 695 break; 696 } 697 case Mips::PseudoMULTu: { 698 MCInst TmpInst; 699 MCOperand MCOp; 700 TmpInst.setOpcode(Mips::MULTu); 701 // Operand: rs 702 lowerOperand(MI->getOperand(1), MCOp); 703 TmpInst.addOperand(MCOp); 704 // Operand: rt 705 lowerOperand(MI->getOperand(2), MCOp); 706 TmpInst.addOperand(MCOp); 707 EmitToStreamer(OutStreamer, TmpInst); 708 break; 709 } 710 case Mips::PseudoPICK_PH: { 711 MCInst TmpInst; 712 MCOperand MCOp; 713 TmpInst.setOpcode(Mips::PICK_PH); 714 // Operand: rd 715 lowerOperand(MI->getOperand(0), MCOp); 716 TmpInst.addOperand(MCOp); 717 // Operand: rs 718 lowerOperand(MI->getOperand(2), MCOp); 719 TmpInst.addOperand(MCOp); 720 // Operand: rt 721 lowerOperand(MI->getOperand(3), MCOp); 722 TmpInst.addOperand(MCOp); 723 EmitToStreamer(OutStreamer, TmpInst); 724 break; 725 } 726 case Mips::PseudoPICK_QB: { 727 MCInst TmpInst; 728 MCOperand MCOp; 729 TmpInst.setOpcode(Mips::PICK_QB); 730 // Operand: rd 731 lowerOperand(MI->getOperand(0), MCOp); 732 TmpInst.addOperand(MCOp); 733 // Operand: rs 734 lowerOperand(MI->getOperand(2), MCOp); 735 TmpInst.addOperand(MCOp); 736 // Operand: rt 737 lowerOperand(MI->getOperand(3), MCOp); 738 TmpInst.addOperand(MCOp); 739 EmitToStreamer(OutStreamer, TmpInst); 740 break; 741 } 742 case Mips::PseudoSDIV: { 743 MCInst TmpInst; 744 MCOperand MCOp; 745 TmpInst.setOpcode(Mips::SDIV); 746 // Operand: rs 747 lowerOperand(MI->getOperand(1), MCOp); 748 TmpInst.addOperand(MCOp); 749 // Operand: rt 750 lowerOperand(MI->getOperand(2), MCOp); 751 TmpInst.addOperand(MCOp); 752 EmitToStreamer(OutStreamer, TmpInst); 753 break; 754 } 755 case Mips::PseudoUDIV: { 756 MCInst TmpInst; 757 MCOperand MCOp; 758 TmpInst.setOpcode(Mips::UDIV); 759 // Operand: rs 760 lowerOperand(MI->getOperand(1), MCOp); 761 TmpInst.addOperand(MCOp); 762 // Operand: rt 763 lowerOperand(MI->getOperand(2), MCOp); 764 TmpInst.addOperand(MCOp); 765 EmitToStreamer(OutStreamer, TmpInst); 766 break; 767 } 768 case Mips::SDIV_MM_Pseudo: { 769 MCInst TmpInst; 770 MCOperand MCOp; 771 TmpInst.setOpcode(Mips::SDIV_MM); 772 // Operand: rs 773 lowerOperand(MI->getOperand(1), MCOp); 774 TmpInst.addOperand(MCOp); 775 // Operand: rt 776 lowerOperand(MI->getOperand(2), MCOp); 777 TmpInst.addOperand(MCOp); 778 EmitToStreamer(OutStreamer, TmpInst); 779 break; 780 } 781 case Mips::TAILCALL: { 782 MCInst TmpInst; 783 MCOperand MCOp; 784 TmpInst.setOpcode(Mips::J); 785 // Operand: target 786 lowerOperand(MI->getOperand(0), MCOp); 787 TmpInst.addOperand(MCOp); 788 EmitToStreamer(OutStreamer, TmpInst); 789 break; 790 } 791 case Mips::TAILCALL64R6REG: { 792 MCInst TmpInst; 793 MCOperand MCOp; 794 TmpInst.setOpcode(Mips::JALR64); 795 // Operand: rd 796 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO_64)); 797 // Operand: rs 798 lowerOperand(MI->getOperand(0), MCOp); 799 TmpInst.addOperand(MCOp); 800 EmitToStreamer(OutStreamer, TmpInst); 801 break; 802 } 803 case Mips::TAILCALLHB64R6REG: { 804 MCInst TmpInst; 805 MCOperand MCOp; 806 TmpInst.setOpcode(Mips::JR_HB64_R6); 807 // Operand: rs 808 lowerOperand(MI->getOperand(0), MCOp); 809 TmpInst.addOperand(MCOp); 810 EmitToStreamer(OutStreamer, TmpInst); 811 break; 812 } 813 case Mips::TAILCALLHBR6REG: { 814 MCInst TmpInst; 815 MCOperand MCOp; 816 TmpInst.setOpcode(Mips::JR_HB_R6); 817 // Operand: rs 818 lowerOperand(MI->getOperand(0), MCOp); 819 TmpInst.addOperand(MCOp); 820 EmitToStreamer(OutStreamer, TmpInst); 821 break; 822 } 823 case Mips::TAILCALLR6REG: { 824 MCInst TmpInst; 825 MCOperand MCOp; 826 TmpInst.setOpcode(Mips::JALR); 827 // Operand: rd 828 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); 829 // Operand: rs 830 lowerOperand(MI->getOperand(0), MCOp); 831 TmpInst.addOperand(MCOp); 832 EmitToStreamer(OutStreamer, TmpInst); 833 break; 834 } 835 case Mips::TAILCALLREG: { 836 MCInst TmpInst; 837 MCOperand MCOp; 838 TmpInst.setOpcode(Mips::JR); 839 // Operand: rs 840 lowerOperand(MI->getOperand(0), MCOp); 841 TmpInst.addOperand(MCOp); 842 EmitToStreamer(OutStreamer, TmpInst); 843 break; 844 } 845 case Mips::TAILCALLREG64: { 846 MCInst TmpInst; 847 MCOperand MCOp; 848 TmpInst.setOpcode(Mips::JR64); 849 // Operand: rs 850 lowerOperand(MI->getOperand(0), MCOp); 851 TmpInst.addOperand(MCOp); 852 EmitToStreamer(OutStreamer, TmpInst); 853 break; 854 } 855 case Mips::TAILCALLREGHB: { 856 MCInst TmpInst; 857 MCOperand MCOp; 858 TmpInst.setOpcode(Mips::JR_HB); 859 // Operand: rs 860 lowerOperand(MI->getOperand(0), MCOp); 861 TmpInst.addOperand(MCOp); 862 EmitToStreamer(OutStreamer, TmpInst); 863 break; 864 } 865 case Mips::TAILCALLREGHB64: { 866 MCInst TmpInst; 867 MCOperand MCOp; 868 TmpInst.setOpcode(Mips::JR_HB64); 869 // Operand: rs 870 lowerOperand(MI->getOperand(0), MCOp); 871 TmpInst.addOperand(MCOp); 872 EmitToStreamer(OutStreamer, TmpInst); 873 break; 874 } 875 case Mips::TAILCALLREG_MM: { 876 MCInst TmpInst; 877 MCOperand MCOp; 878 TmpInst.setOpcode(Mips::JRC16_MM); 879 // Operand: rs 880 lowerOperand(MI->getOperand(0), MCOp); 881 TmpInst.addOperand(MCOp); 882 EmitToStreamer(OutStreamer, TmpInst); 883 break; 884 } 885 case Mips::TAILCALLREG_MMR6: { 886 MCInst TmpInst; 887 MCOperand MCOp; 888 TmpInst.setOpcode(Mips::JRC16_MM); 889 // Operand: rs 890 lowerOperand(MI->getOperand(0), MCOp); 891 TmpInst.addOperand(MCOp); 892 EmitToStreamer(OutStreamer, TmpInst); 893 break; 894 } 895 case Mips::TAILCALL_MM: { 896 MCInst TmpInst; 897 MCOperand MCOp; 898 TmpInst.setOpcode(Mips::J_MM); 899 // Operand: target 900 lowerOperand(MI->getOperand(0), MCOp); 901 TmpInst.addOperand(MCOp); 902 EmitToStreamer(OutStreamer, TmpInst); 903 break; 904 } 905 case Mips::TAILCALL_MMR6: { 906 MCInst TmpInst; 907 MCOperand MCOp; 908 TmpInst.setOpcode(Mips::BC_MMR6); 909 // Operand: offset 910 lowerOperand(MI->getOperand(0), MCOp); 911 TmpInst.addOperand(MCOp); 912 EmitToStreamer(OutStreamer, TmpInst); 913 break; 914 } 915 case Mips::TRAP: { 916 MCInst TmpInst; 917 MCOperand MCOp; 918 TmpInst.setOpcode(Mips::BREAK); 919 // Operand: code_1 920 TmpInst.addOperand(MCOperand::createImm(0)); 921 // Operand: code_2 922 TmpInst.addOperand(MCOperand::createImm(0)); 923 EmitToStreamer(OutStreamer, TmpInst); 924 break; 925 } 926 case Mips::TRAP_MM: { 927 MCInst TmpInst; 928 MCOperand MCOp; 929 TmpInst.setOpcode(Mips::BREAK_MM); 930 // Operand: code_1 931 TmpInst.addOperand(MCOperand::createImm(0)); 932 // Operand: code_2 933 TmpInst.addOperand(MCOperand::createImm(0)); 934 EmitToStreamer(OutStreamer, TmpInst); 935 break; 936 } 937 case Mips::UDIV_MM_Pseudo: { 938 MCInst TmpInst; 939 MCOperand MCOp; 940 TmpInst.setOpcode(Mips::UDIV_MM); 941 // Operand: rs 942 lowerOperand(MI->getOperand(1), MCOp); 943 TmpInst.addOperand(MCOp); 944 // Operand: rt 945 lowerOperand(MI->getOperand(2), MCOp); 946 TmpInst.addOperand(MCOp); 947 EmitToStreamer(OutStreamer, TmpInst); 948 break; 949 } 950 case Mips::XOR_V_D_PSEUDO: { 951 MCInst TmpInst; 952 MCOperand MCOp; 953 TmpInst.setOpcode(Mips::XOR_V); 954 // Operand: wd 955 lowerOperand(MI->getOperand(0), MCOp); 956 TmpInst.addOperand(MCOp); 957 // Operand: ws 958 lowerOperand(MI->getOperand(1), MCOp); 959 TmpInst.addOperand(MCOp); 960 // Operand: wt 961 lowerOperand(MI->getOperand(2), MCOp); 962 TmpInst.addOperand(MCOp); 963 EmitToStreamer(OutStreamer, TmpInst); 964 break; 965 } 966 case Mips::XOR_V_H_PSEUDO: { 967 MCInst TmpInst; 968 MCOperand MCOp; 969 TmpInst.setOpcode(Mips::XOR_V); 970 // Operand: wd 971 lowerOperand(MI->getOperand(0), MCOp); 972 TmpInst.addOperand(MCOp); 973 // Operand: ws 974 lowerOperand(MI->getOperand(1), MCOp); 975 TmpInst.addOperand(MCOp); 976 // Operand: wt 977 lowerOperand(MI->getOperand(2), MCOp); 978 TmpInst.addOperand(MCOp); 979 EmitToStreamer(OutStreamer, TmpInst); 980 break; 981 } 982 case Mips::XOR_V_W_PSEUDO: { 983 MCInst TmpInst; 984 MCOperand MCOp; 985 TmpInst.setOpcode(Mips::XOR_V); 986 // Operand: wd 987 lowerOperand(MI->getOperand(0), MCOp); 988 TmpInst.addOperand(MCOp); 989 // Operand: ws 990 lowerOperand(MI->getOperand(1), MCOp); 991 TmpInst.addOperand(MCOp); 992 // Operand: wt 993 lowerOperand(MI->getOperand(2), MCOp); 994 TmpInst.addOperand(MCOp); 995 EmitToStreamer(OutStreamer, TmpInst); 996 break; 997 } 998 } 999 return true; 1000} 1001 1002