| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | atomicrmx.ll | 13 ;CHK32: LL_R6
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| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | atomicrmx.ll | 13 ;CHK32: LL_R6
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 97 LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in expandAtomicCmpSwapSubword()
224 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in expandAtomicCmpSwap()
321 LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in expandAtomicBinOpSubword()
501 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in expandAtomicBinOp()
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| D | MipsSERegisterInfo.cpp | 96 case Mips::LL_R6: in getLoadStoreOffsetSizeInBits()
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| D | Mips32r6InstrInfo.td | 912 def LL_R6 : LL_R6_ENC, LL_R6_DESC, PTR_32, ISA_MIPS32R6;
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 220 case Mips::LL_R6: in isBasePlusOffsetMemoryAccess()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 229 case Mips::LL_R6: in isBasePlusOffsetMemoryAccess()
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| /external/v8/src/mips/ |
| D | constants-mips.h | 569 LL_R6 = ((6U << 3) + 6), enumerator
1735 case LL_R6: in InstructionType()
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| D | disasm-mips.cc | 1677 case LL_R6: { in DecodeTypeImmediateSPECIAL3()
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| D | assembler-mips.cc | 2304 GenInstrImmediate(SPECIAL3, rs.rm(), rd, rs.offset_, 0, LL_R6); in ll()
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| D | simulator-mips.cc | 6808 case LL_R6: { in DecodeTypeImmediate()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 589 LL_R6 = ((6U << 3) + 6), enumerator
1800 case LL_R6: in InstructionType()
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| D | disasm-mips64.cc | 1971 case LL_R6: { in DecodeTypeImmediateSPECIAL3()
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| D | assembler-mips64.cc | 2457 GenInstrImmediate(SPECIAL3, rs.rm(), rd, rs.offset_, 0, LL_R6); in ll()
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| D | simulator-mips64.cc | 7139 case LL_R6: { in DecodeTypeImmediate()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1122 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in emitAtomicBinary()
1268 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in emitAtomicBinaryPartword()
1410 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in emitAtomicCmpSwap()
1523 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in emitAtomicCmpSwapPartword()
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| D | Mips32r6InstrInfo.td | 798 def LL_R6 : LL_R6_ENC, LL_R6_DESC, PTR_32, ISA_MIPS32R6;
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 952 12604977U, // LL_R6
2666 0U, // LL_R6
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| D | MipsGenDisassemblerTables.inc | 4025 /* 1651 */ MCD_OPC_Decode, 167, 7, 223, 1, // Opcode: LL_R6
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1684 UINT64_C(2080374838), // LL_R6
5603 case Mips::LL_R6: {
9410 …_HasStdEnc | Feature_IsPTR32bit | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // LL_R6 = 1671
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| D | MipsGenAsmWriter.inc | 2899 25188499U, // LL_R6
5530 0U, // LL_R6
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| D | MipsGenInstrInfo.inc | 1686 LL_R6 = 1671,
5731 …modeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1671 = LL_R6
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| D | MipsGenDisassemblerTables.inc | 6609 /* 2094 */ MCD::OPC_Decode, 135, 13, 228, 2, // Opcode: LL_R6
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| D | MipsGenAsmMatcher.inc | 6482 …{ 5552 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Featur…
|