| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 411 LWC1 = 4, enumerator
825 return Latency::LWC1; in Ulwc1Latency()
840 int latency = AdjustBaseAndOffsetLatency() + Latency::LWC1; in Ldc1Latency()
842 return latency + Latency::LWC1; in Ldc1Latency()
1596 return Latency::LWC1; in GetInstructionLatency()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 54 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) || in isLoadFromStackSlot()
205 Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1; in loadRegFromStackSlot()
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| D | MipsInstrFPU.td | 201 def LWC1 : FPLoad<0x31, "lwc1", load, FGR32, mem>;
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 217 case Mips::LWC1: in isBasePlusOffsetMemoryAccess()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 226 case Mips::LWC1: in isBasePlusOffsetMemoryAccess()
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| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 444 LWC1 = 4, enumerator
794 int Lwc1Latency() { return AdjustBaseAndOffsetLatency() + Latency::LWC1; } in Lwc1Latency()
1615 latency = Latency::LWC1; in GetInstructionLatency()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/MIR/Mips/ |
| D | live-debug-values-reg-copy.mir | 199 …renamable $f1 = LWC1 killed renamable $at_64, target-flags(mips-abs-lo) %const.2, debug-location !…
212 …renamable $f0 = LWC1 killed renamable $at_64, target-flags(mips-abs-lo) %const.1, debug-location !…
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
278 Opc = Mips::LWC1; in loadRegFromStack()
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| D | MipsInstrFPU.td | 404 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>,
647 def : LoadRegImmPat<LWC1, f32, load>;
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| D | MipsFastISel.cpp | 743 Opc = Mips::LWC1; in emitLoad()
|
| /external/v8/src/mips/ |
| D | constants-mips.h | 472 LWC1 = ((6U << 3) + 1) << kOpcodeShift, enumerator
1273 OpcodeToBitNumber(LWC1) | OpcodeToBitNumber(LDC1) |
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| D | disasm-mips.cc | 1961 case LWC1: in DecodeTypeImmediate()
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| D | assembler-mips.cc | 2589 GenInstrImmediate(LWC1, tmp.rm(), fd, tmp.offset()); in lwc1()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 450 LWC1 = ((6U << 3) + 1) << kOpcodeShift, enumerator
1309 OpcodeToBitNumber(LWC1) | OpcodeToBitNumber(LDC1) |
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| D | disasm-mips64.cc | 2261 case LWC1: in DecodeTypeImmediate()
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| D | assembler-mips64.cc | 2970 GenInstrImmediate(LWC1, src.rm(), fd, src.offset_); in lwc1()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 51 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
351 Opc = Mips::LWC1; in loadRegFromStack()
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| D | MipsInstrFPU.td | 533 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>,
778 <"l.s $fd, $addr", (LWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>,
927 def : LoadRegImmPat<LWC1, f32, load>, ISA_MIPS1;
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| D | MipsScheduleP5600.td | 566 def : InstRW<[P5600WriteLoadFPU], (instrs LDC1, LDXC1, LWC1, LWXC1, LUXC1)>;
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| D | MipsFastISel.cpp | 778 Opc = Mips::LWC1; in emitLoad()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| D | target-soft-float.s | 274 # FIXME: LWC1 is correctly rejected but the wrong error message is emitted.
|
| /external/llvm/test/MC/Mips/ |
| D | target-soft-float.s | 274 # FIXME: LWC1 is correctly rejected but the wrong error message is emitted.
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 958 {DBGFIELD("LWC1") 1, false, false, 26, 2, 2, 1, 0, 0}, // #683
1978 {DBGFIELD("LWC1") 2, false, false, 77, 4, 6, 1, 0, 0}, // #683
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| D | MipsGenMCCodeEmitter.inc | 1698 UINT64_C(3288334336), // LWC1
5635 case Mips::LWC1:
9424 Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // LWC1 = 1685
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 970 12599389U, // LWC1
2684 0U, // LWC1
|