| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | unaligned-memops.ll | 15 ; MIPS: [[LWL:%[0-9]+]]:gpr32 = LWL [[COPY1]], 0, [[DEF]] :: (load 4 from %ir.a, align 1)
16 ; MIPS: [[LWR:%[0-9]+]]:gpr32 = LWR [[COPY1]], 3, [[LWL]] :: (load 4 from %ir.a, align 1)
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| D | unaligned-memops-mapping.mir | 60 %2:gpr32 = LWL %0, 0, %3 :: (load 4 from %ir.a, align 1)
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 221 case Mips::LWL: in isBasePlusOffsetMemoryAccess()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 230 case Mips::LWL: in isBasePlusOffsetMemoryAccess()
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| /external/v8/src/mips/ |
| D | constants-mips.h | 460 LWL = ((4U << 3) + 2) << kOpcodeShift, enumerator
1269 OpcodeToBitNumber(LB) | OpcodeToBitNumber(LH) | OpcodeToBitNumber(LWL) |
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| D | disasm-mips.cc | 1914 case LWL: in DecodeTypeImmediate()
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| D | assembler-mips.cc | 2253 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); in lwl()
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| D | simulator-mips.cc | 6667 case LWL: { in DecodeTypeImmediate()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 434 LWL = ((4U << 3) + 2) << kOpcodeShift, enumerator
1303 OpcodeToBitNumber(LWL) | OpcodeToBitNumber(LW) | OpcodeToBitNumber(LWU) |
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| D | disasm-mips64.cc | 2179 case LWL: in DecodeTypeImmediate()
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| D | assembler-mips64.cc | 2415 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); in lwl()
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| D | simulator-mips64.cc | 6915 case LWL: { in DecodeTypeImmediate()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 202 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, enumerator
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| D | MipsISelLowering.cpp | 147 case MipsISD::LWL: return "MipsISD::LWL"; in getTargetNodeName()
2294 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, in lowerLOAD() local
2296 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, in lowerLOAD()
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| D | MipsInstrInfo.td | 132 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
1767 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 248 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, enumerator
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| D | MipsISelLowering.cpp | 229 case MipsISD::LWL: return "MipsISD::LWL"; in getTargetNodeName()
2487 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, in lowerLOAD() local
2489 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, in lowerLOAD()
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| D | MipsScheduleP5600.td | 127 def : InstRW<[P5600WriteLoadShifted], (instrs LWL, LWR, LWLE, LWRE)>;
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| D | MipsInstrInfo.td | 139 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
2119 def LWL : MMRel, LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 704 {DBGFIELD("LWL") 1, false, false, 17, 2, 2, 1, 0, 0}, // #429
1724 {DBGFIELD("LWL") 1, false, false, 43, 3, 6, 1, 0, 0}, // #429
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| D | MipsGenMCCodeEmitter.inc | 1709 UINT64_C(2281701376), // LWL
5639 case Mips::LWL:
9435 …e_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // LWL = 1696
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| D | MipsGenInstrInfo.inc | 1711 LWL = 1696,
3086 LWL = 429,
5756 …1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1696 = LWL
10164 { Mips::LWL, Mips::LWL, Mips::LWL_MM },
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| D | MipsGenAsmWriter.inc | 2924 25188607U, // LWL
5555 0U, // LWL
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 975 12605051U, // LWL
2689 0U, // LWL
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3306 TOut.emitRRI(Mips::LWL, DstRegOp.getReg(), FinalSrcReg, LeftLoadOffset, IDLoc, in expandUlw()
|