| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | unaligned-memops.ll | 16 ; MIPS: [[LWR:%[0-9]+]]:gpr32 = LWR [[COPY1]], 3, [[LWL]] :: (load 4 from %ir.a, align 1)
17 ; MIPS: SWL [[LWR]], [[COPY]], 0 :: (store 4 into %ir.b, align 1)
18 ; MIPS: SWR [[LWR]], [[COPY]], 3 :: (store 4 into %ir.b, align 1)
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| D | unaligned-memops-mapping.mir | 61 %4:gpr32 = LWR %0, 3, %2 :: (load 4 from %ir.a, align 1)
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 222 case Mips::LWR: in isBasePlusOffsetMemoryAccess()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 231 case Mips::LWR: in isBasePlusOffsetMemoryAccess()
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| /external/v8/src/mips/ |
| D | constants-mips.h | 464 LWR = ((4U << 3) + 6) << kOpcodeShift, enumerator
1271 OpcodeToBitNumber(LWR) | OpcodeToBitNumber(SB) | OpcodeToBitNumber(SH) |
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| D | disasm-mips.cc | 1926 case LWR: in DecodeTypeImmediate()
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| D | assembler-mips.cc | 2261 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_); in lwr()
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| D | simulator-mips.cc | 6688 case LWR: { in DecodeTypeImmediate()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 438 LWR = ((4U << 3) + 6) << kOpcodeShift, enumerator
1305 OpcodeToBitNumber(LDL) | OpcodeToBitNumber(LDR) | OpcodeToBitNumber(LWR) |
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| D | disasm-mips64.cc | 2200 case LWR: in DecodeTypeImmediate()
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| D | assembler-mips64.cc | 2422 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_); in lwr()
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| D | simulator-mips64.cc | 6942 case LWR: { in DecodeTypeImmediate()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 203 LWR, enumerator
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| D | MipsISelLowering.cpp | 148 case MipsISD::LWR: return "MipsISD::LWR"; in getTargetNodeName()
2296 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, in lowerLOAD() local
2308 return LWR; in lowerLOAD()
2321 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); in lowerLOAD()
2323 SDValue Ops[] = { SRL, LWR.getValue(1) }; in lowerLOAD()
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| D | MipsInstrInfo.td | 134 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
1769 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.cpp | 375 case 0x1: return MBlaze::LWR; in decodeLW()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 249 LWR, enumerator
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| D | MipsISelLowering.cpp | 230 case MipsISD::LWR: return "MipsISD::LWR"; in getTargetNodeName()
2489 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, in lowerLOAD() local
2501 return LWR; in lowerLOAD()
2514 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); in lowerLOAD()
2516 SDValue Ops[] = { SRL, LWR.getValue(1) }; in lowerLOAD()
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| D | MipsScheduleP5600.td | 127 def : InstRW<[P5600WriteLoadShifted], (instrs LWL, LWR, LWLE, LWRE)>;
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| D | MipsInstrInfo.td | 141 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
2121 def LWR : MMRel, LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.td | 453 def LWR : LoadM<0x32, 0x200, "lwr ">;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 705 {DBGFIELD("LWR") 1, false, false, 17, 2, 2, 1, 0, 0}, // #430
1725 {DBGFIELD("LWR") 1, false, false, 43, 3, 6, 1, 0, 0}, // #430
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| D | MipsGenMCCodeEmitter.inc | 1720 UINT64_C(2550136832), // LWR
5641 case Mips::LWR:
9446 …e_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // LWR = 1707
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 979 12605430U, // LWR
2693 0U, // LWR
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3309 TOut.emitRRI(Mips::LWR, DstRegOp.getReg(), FinalSrcReg, RightLoadOffset, in expandUlw()
|