| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-misched-basic-A53.ll | 5 ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
7 ; specifying a subtarget, the MADD will remain near the end of the block.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-misched-basic-A53.ll | 5 ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
7 ; specifying a subtarget, the MADD will remain near the end of the block.
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_64.c | 104 #define MADD 0x9b000000 macro
763 return push_inst(compiler, (MADD ^ inv_bits) | RD(dst) | RN(arg1) | RM(arg2) | RT2(TMP_ZERO)); in emit_op_imm()
770 FAIL_IF(push_inst(compiler, MADD | RD(dst) | RN(arg1) | RM(arg2) | RT2(TMP_ZERO))); in emit_op_imm()
1097 FAIL_IF(push_inst(compiler, MADD | RD(SLJIT_R0) | RN(SLJIT_R0) | RM(SLJIT_R1) | RT2(TMP_ZERO))); in sljit_emit_op0()
1103 …FAIL_IF(push_inst(compiler, (MADD ^ inv_bits) | RD(SLJIT_R1) | RN(SLJIT_R0) | RM(SLJIT_R1) | RT2(T… in sljit_emit_op0()
|
| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 305 MADD = 4, enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 807 // MADD*/MSUB*
808 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 403 (instregex "MADD(HD|HDU|LD)$"),
477 (instregex "F(N)?MADD(S)?o$"),
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 635 TmpInst.setOpcode(Mips::MADD);
|
| D | MipsGenMCCodeEmitter.inc | 1747 UINT64_C(1879048192), // MADD
5182 case Mips::MADD:
9473 …_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MADD = 1734
|
| D | MipsGenAsmWriter.inc | 2962 20512U, // MADD
5593 0U, // MADD
|
| D | MipsGenInstrInfo.inc | 1749 MADD = 1734,
5794 …Effects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1734 = MADD
10170 { Mips::MADD, Mips::MADD, Mips::MADD_MM },
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 188 def : InstRW<[P5600WriteAL2MAdd], (instrs MADD, MADDU, MSUB, MSUBU,
|
| D | MipsInstrInfo.td | 2375 // MADD*/MSUB*
2376 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
2394 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 189 // MUL/MNEG are aliases for MADD/MSUB.
|
| D | AArch64InstrInfo.td | 718 defm MADD : MulAccum<0, "madd", add>;
|
| D | AArch64InstrFormats.td | 1449 // MADD/MSUB generation is decided by MachineCombiner.cpp
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 191 // MUL/MNEG are aliases for MADD/MSUB.
|
| D | AArch64InstrInfo.td | 917 defm MADD : MulAccum<0, "madd", add>;
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 2008 // MADD*/MSUB*
2009 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
2026 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1080 MADD = MADD_w, enumerator
|
| D | assembler-arm64.cc | 1451 DataProcessing3Source(rd, rn, rm, zr, MADD); in mul()
1460 DataProcessing3Source(rd, rn, rm, ra, MADD); in madd()
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1005 20034U, // MADD
2719 0U, // MADD
4859 // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD...
|
| D | MipsGenDisassemblerTables.inc | 1266 /* 3571 */ MCD_OPC_Decode, 220, 7, 24, // Opcode: MADD
|
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1253 MADD = MADD_w, enumerator
|
| D | assembler-aarch64.cc | 881 DataProcessing3Source(rd, rn, rm, AppropriateZeroRegFor(rd), MADD); in mul()
889 DataProcessing3Source(rd, rn, rm, ra, MADD); in madd()
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 763 ### MADD ### subsection
|