Home
last modified time | relevance | path

Searched refs:MCPhysReg (Results 1 – 25 of 282) sorted by relevance

12345678910>>...12

/external/capstone/arch/X86/
DX86GenRegisterInfo.inc342 static MCPhysReg X86RegDiffLists[] = {
638 static MCPhysReg GR8[] = {
648 static MCPhysReg GR8_NOREX[] = {
658 static MCPhysReg GR8_ABCD_H[] = {
668 static MCPhysReg GR8_ABCD_L[] = {
678 static MCPhysReg GR16[] = {
688 static MCPhysReg GR16_NOREX[] = {
698 static MCPhysReg VK1[] = {
708 static MCPhysReg VK16[] = {
718 static MCPhysReg VK2[] = {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/
DMCInstrDescView.cpp38 for (const llvm::MCPhysReg *MCPhysReg = MCInstrDesc.getImplicitDefs(); in Instruction() local
39 MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) { in Instruction()
44 Operand.Tracker = &RATC.getRegister(*MCPhysReg); in Instruction()
45 Operand.ImplicitReg = MCPhysReg; in Instruction()
48 for (const llvm::MCPhysReg *MCPhysReg = MCInstrDesc.getImplicitUses(); in Instruction() local
49 MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) { in Instruction()
54 Operand.Tracker = &RATC.getRegister(*MCPhysReg); in Instruction()
55 Operand.ImplicitReg = MCPhysReg; in Instruction()
164 const llvm::MCPhysReg Reg, bool SelectDef, llvm::ArrayRef<Operand> Operands, in addOperandIfAlias()
196 for (const llvm::MCPhysReg Reg : CommonRegisters.set_bits()) { in AliasingConfigurations()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc136 static const MCPhysReg RegList1[] = {
139 static const MCPhysReg RegList2[] = {
150 static const MCPhysReg RegList3[] = {
153 static const MCPhysReg RegList4[] = {
165 static const MCPhysReg ShadowRegList5[] = {
175 static const MCPhysReg RegList7[] = {
178 static const MCPhysReg RegList8[] = {
188 static const MCPhysReg RegList9[] = {
191 static const MCPhysReg RegList10[] = {
201 static const MCPhysReg RegList11[] = {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMCallingConv.h31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
75 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
76 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
77 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
126 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
127 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
163 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
165 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
169 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
[all …]
/external/llvm/lib/Target/ARM/
DARMCallingConv.h31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
75 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
76 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
77 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
126 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
127 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
163 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
165 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
169 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
[all …]
/external/capstone/
DMCRegisterInfo.c25 MCPhysReg *List;
33 MCPhysReg *DL, in MCRegisterInfo_InitMCRegisterInfo()
53 static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, MCPhysReg *DiffList) in DiffListIterator_init()
66 MCPhysReg D; in DiffListIterator_next()
94 DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs); in MCRegisterInfo_getMatchingSuperReg()
113 DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs); in MCRegisterInfo_getSubReg()
DMCRegisterInfo.h29 typedef uint16_t MCPhysReg; typedef
30 typedef MCPhysReg* iterator;
86 MCPhysReg *DiffLists; // Pointer to the difflists array
101 MCPhysReg *DL,
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp55 const MCPhysReg *
60 static const MCPhysReg Int32[] = { in getCallerSavedRegs()
63 static const MCPhysReg Int64[] = { in getCallerSavedRegs()
66 static const MCPhysReg Pred[] = { in getCallerSavedRegs()
69 static const MCPhysReg VecSgl[] = { in getCallerSavedRegs()
74 static const MCPhysReg VecDbl[] = { in getCallerSavedRegs()
95 static const MCPhysReg Empty[] = { 0 }; in getCallerSavedRegs()
104 const MCPhysReg *
106 static const MCPhysReg CalleeSavedRegsV3[] = { in getCalleeSavedRegs()
114 static const MCPhysReg CalleeSavedRegsV3EHReturn[] = { in getCalleeSavedRegs()
/external/capstone/arch/SystemZ/
DSystemZGenRegisterInfo.inc160 static MCPhysReg SystemZRegDiffLists[] = {
316 static MCPhysReg GRX32Bit[] = {
326 static MCPhysReg FP32Bit[] = {
336 static MCPhysReg GR32Bit[] = {
346 static MCPhysReg GRH32Bit[] = {
356 static MCPhysReg ADDR32Bit[] = {
366 static MCPhysReg CCRegs[] = {
376 static MCPhysReg FP64Bit[] = {
386 static MCPhysReg GR64Bit[] = {
396 static MCPhysReg ADDR64Bit[] = {
[all …]
/external/capstone/arch/Mips/
DMipsGenRegisterInfo.inc500 static MCPhysReg MipsRegDiffLists[] = {
997 static MCPhysReg OddSP[] = {
1007 static MCPhysReg CCR[] = {
1017 static MCPhysReg COP2[] = {
1027 static MCPhysReg COP3[] = {
1037 static MCPhysReg DSPR[] = {
1047 static MCPhysReg FGR32[] = {
1057 static MCPhysReg FGRCC[] = {
1067 static MCPhysReg FGRH32[] = {
1077 static MCPhysReg GPR32[] = {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86CallingConv.cpp27 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs()
61 static ArrayRef<MCPhysReg> CC_X86_VectorCallGetSSEs(const MVT &ValVT) { in CC_X86_VectorCallGetSSEs()
63 static const MCPhysReg RegListZMM[] = {X86::ZMM0, X86::ZMM1, X86::ZMM2, in CC_X86_VectorCallGetSSEs()
69 static const MCPhysReg RegListYMM[] = {X86::YMM0, X86::YMM1, X86::YMM2, in CC_X86_VectorCallGetSSEs()
74 static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2, in CC_X86_VectorCallGetSSEs()
79 static ArrayRef<MCPhysReg> CC_X86_64_VectorCallGetGPRs() { in CC_X86_64_VectorCallGetGPRs()
80 static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9}; in CC_X86_64_VectorCallGetGPRs()
90 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister()
DShadowCallStack.cpp70 MCPhysReg FreeRegister);
76 MCPhysReg FreeRegister);
84 addSegmentedMem(const MachineInstrBuilder &MIB, MCPhysReg Seg, MCPhysReg Reg, in addSegmentedMem()
91 const MCPhysReg ReturnReg = X86::R10; in addProlog()
92 const MCPhysReg OffsetReg = X86::R11; in addProlog()
119 MCPhysReg FreeRegister) { in addPrologLeaf()
156 MCPhysReg FreeRegister) { in addEpilogLeaf()
237 MCPhysReg LeafFuncRegister = X86::NoRegister; in runOnMachineFunction()
257 const MCPhysReg *CSRegs = Fn.getRegInfo().getCalleeSavedRegs(); in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64RedundantCopyElimination.cpp89 MCPhysReg Reg;
91 RegImm(MCPhysReg Reg, int32_t Imm) : Reg(Reg), Imm(Imm) {} in RegImm()
187 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock()
188 MCPhysReg SrcReg = PredI.getOperand(1).getReg(); in knownRegValInBlock()
253 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock()
325 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock()
326 MCPhysReg CopySrcReg = PredI->getOperand(1).getReg(); in optimizeBlock()
383 MCPhysReg DefReg = MI->getOperand(0).getReg(); in optimizeBlock()
384 MCPhysReg SrcReg = IsCopy ? MI->getOperand(1).getReg() : 0; in optimizeBlock()
406 MCPhysReg CmpReg = KnownReg.Reg; in optimizeBlock()
[all …]
DAArch64CallingConvention.h28 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
31 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
34 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
37 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
40 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
89 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h38 std::unique_ptr<MCPhysReg[]> Order;
42 operator ArrayRef<MCPhysReg>() const {
60 const MCPhysReg *CalleeSavedRegs = nullptr;
63 SmallVector<MCPhysReg, 4> CalleeSavedAliases;
97 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenCallingConv.inc134 static const MCPhysReg RegList1[] = {
137 static const MCPhysReg RegList2[] = {
149 static const MCPhysReg RegList3[] = {
161 static const MCPhysReg ShadowRegList4[] = {
171 static const MCPhysReg ShadowRegList6[] = {
180 static const MCPhysReg ShadowRegList8[] = {
189 static const MCPhysReg ShadowRegList10[] = {
199 static const MCPhysReg ShadowRegList12[] = {
209 static const MCPhysReg ShadowRegList14[] = {
274 static const MCPhysReg RegList1[] = {
[all …]
/external/capstone/arch/PowerPC/
DPPCGenRegisterInfo.inc350 static MCPhysReg PPCRegDiffLists[] = {
684 static MCPhysReg GPRC[] = {
694 static MCPhysReg GPRC_NOR0[] = {
704 static MCPhysReg GPRC_and_GPRC_NOR0[] = {
714 static MCPhysReg CRBITRC[] = {
724 static MCPhysReg F4RC[] = {
734 static MCPhysReg CRRC[] = {
744 static MCPhysReg CARRYRC[] = {
754 static MCPhysReg CCRC[] = {
764 static MCPhysReg CTRRC[] = {
[all …]
/external/llvm/include/llvm/MC/
DMCRegisterInfo.h27 typedef uint16_t MCPhysReg; typedef
32 typedef const MCPhysReg* iterator;
33 typedef const MCPhysReg* const_iterator;
162 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
163 const MCPhysReg *DiffLists; // Pointer to the difflists array
194 const MCPhysReg *List;
203 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) { in init()
213 MCPhysReg D = *List++; in advance()
248 const MCPhysReg (*RURoots)[2], in InitMCRegisterInfo()
250 const MCPhysReg *DL, in InitMCRegisterInfo()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCRegisterInfo.h30 using MCPhysReg = uint16_t; variable
35 using iterator = const MCPhysReg*;
36 using const_iterator = const MCPhysReg*;
163 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
164 const MCPhysReg *DiffLists; // Pointer to the difflists array
195 const MCPhysReg *List = nullptr;
204 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) { in init()
214 MCPhysReg D = *List++; in advance()
248 const MCPhysReg (*RURoots)[2], in InitMCRegisterInfo()
250 const MCPhysReg *DL, in InitMCRegisterInfo()
/external/capstone/arch/AArch64/
DAArch64GenRegisterInfo.inc570 static MCPhysReg AArch64RegDiffLists[] = {
1065 static MCPhysReg FPR8[] = {
1075 static MCPhysReg FPR16[] = {
1085 static MCPhysReg GPR32all[] = {
1095 static MCPhysReg FPR32[] = {
1105 static MCPhysReg GPR32[] = {
1115 static MCPhysReg GPR32sp[] = {
1125 static MCPhysReg GPR32common[] = {
1135 static MCPhysReg CCR[] = {
1145 static MCPhysReg GPR32sponly[] = {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DRegAllocFast.cpp87 MCPhysReg PhysReg = 0; ///< Currently held here.
140 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr()
146 bool isRegUsedInInstr(MCPhysReg PhysReg) const { in isRegUsedInInstr()
196 void definePhysReg(MachineBasicBlock::iterator MI, MCPhysReg PhysReg,
198 unsigned calcSpillCost(MCPhysReg PhysReg) const;
199 void assignVirtToPhysReg(LiveReg &, MCPhysReg PhysReg);
209 LiveRegMap::iterator assignVirtToPhysReg(unsigned VirtReg, MCPhysReg PhysReg);
217 bool setPhysReg(MachineInstr &MI, unsigned OpNum, MCPhysReg PhysReg);
399 MCPhysReg Alias = *AI; in usePhysReg()
441 MCPhysReg PhysReg, RegState NewState) { in definePhysReg()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.h28 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
31 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
34 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
37 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
40 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
89 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp55 const MCPhysReg *
60 static const MCPhysReg Int32[] = { in getCallerSavedRegs()
63 static const MCPhysReg Int64[] = { in getCallerSavedRegs()
66 static const MCPhysReg Pred[] = { in getCallerSavedRegs()
69 static const MCPhysReg VecSgl[] = { in getCallerSavedRegs()
74 static const MCPhysReg VecDbl[] = { in getCallerSavedRegs()
93 static const MCPhysReg Empty[] = { 0 }; in getCallerSavedRegs()
102 const MCPhysReg *
104 static const MCPhysReg CalleeSavedRegsV3[] = { in getCalleeSavedRegs()
112 static const MCPhysReg CalleeSavedRegsV3EHReturn[] = { in getCalleeSavedRegs()
/external/capstone/arch/Sparc/
DSparcGenRegisterInfo.inc176 static MCPhysReg SparcRegDiffLists[] = {
372 static MCPhysReg FCCRegs[] = {
382 static MCPhysReg FPRegs[] = {
392 static MCPhysReg IntRegs[] = {
402 static MCPhysReg DFPRegs[] = {
412 static MCPhysReg I64Regs[] = {
422 static MCPhysReg DFPRegs_with_sub_even[] = {
432 static MCPhysReg QFPRegs[] = {
442 static MCPhysReg QFPRegs_with_sub_even[] = {
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc176 static const MCPhysReg RegList1[] = {
188 static const MCPhysReg RegList2[] = {
200 static const MCPhysReg RegList3[] = {
212 static const MCPhysReg RegList4[] = {
234 static const MCPhysReg RegList6[] = {
247 static const MCPhysReg RegList7[] = {
260 static const MCPhysReg RegList8[] = {
398 static const MCPhysReg RegList1[] = {
430 static const MCPhysReg RegList1[] = {
444 static const MCPhysReg RegList2[] = {
[all …]

12345678910>>...12