| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 417 MFC1 = 1, enumerator
635 return Latency::MFC1; in Mfhc1Latency()
672 return Latency::MFC1 + ExtLatency() + Latency::BRANCH + Latency::MOV_S + 4 + in Float32RoundLatency()
673 Latency::MFC1 + Latency::BRANCH + Latency::CVT_S_W; in Float32RoundLatency()
697 int FloorWDLatency() { return Floor_w_dLatency() + Latency::MFC1; } in FloorWDLatency()
707 int CeilWDLatency() { return Ceil_w_dLatency() + Latency::MFC1; } in CeilWDLatency()
717 int RoundWDLatency() { return Round_w_dLatency() + Latency::MFC1; } in RoundWDLatency()
737 Latency::TRUNC_W_D + Latency::MFC1 + OrLatency(false) + in Trunc_uw_dLatency()
738 Latency::BRANCH + Latency::TRUNC_W_D + Latency::MFC1; in Trunc_uw_dLatency()
743 Latency::TRUNC_W_S + Latency::MFC1 + OrLatency(false) + in Trunc_uw_sLatency()
[all …]
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| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 447 MFC1 = 1, enumerator
782 return Latency::MFC1 + UswLatency(); in Uswc1Latency()
903 return 2 + Latency::TRUNC_W_D + Latency::MFC1 + 2 + AndLatency(false) + in TryInlineTruncateDoubleToILatency()
1014 Latency::MFC1 + 1 + XorLatency() + Latency::MTC1; in NegsLatency()
1044 return Latency::MFC1 + 1 + Latency::BRANCH + Latency::MOV_S + 4 + in Float32RoundLatency()
1045 Latency::MFC1 + Latency::BRANCH + Latency::CVT_S_W + 2 + in Float32RoundLatency()
1057 Latency::MFC1 + 1 + Latency::MOV_S; in Float32MaxLatency()
1079 Latency::MFC1 + 1 + Latency::MOV_S; in Float32MinLatency()
1506 return Latency::FLOOR_W_D + Latency::MFC1; in GetInstructionLatency()
1508 return Latency::CEIL_W_D + Latency::MFC1; in GetInstructionLatency()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 106 const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1); in ExpandExtractElementF64()
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| D | MipsInstrFPU.td | 178 def MFC1 : FFRGPR<0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
369 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
370 def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
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| D | MipsInstrInfo.cpp | 114 Opc = Mips::MFC1; in copyPhysReg()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 816 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
848 unsigned MovOpc = Mips::MFC1; in EmitSwapFPIntRetval()
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| D | MipsSEInstrInfo.cpp | 95 Opc = Mips::MFC1; in copyPhysReg()
644 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); in expandExtractElementF64()
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| D | MipsInstrFPU.td | 366 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
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| D | MipsFastISel.cpp | 1080 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 872 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
905 unsigned MovOpc = Mips::MFC1; in EmitSwapFPIntRetval()
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| D | MipsSEInstrInfo.cpp | 100 Opc = Mips::MFC1; in copyPhysReg()
806 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); in expandExtractElementF64()
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| D | MipsScheduleP5600.td | 553 MFC1, MFC1_D64, MFHC1_D32, MFHC1_D64,
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| D | MipsInstrFPU.td | 488 def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
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| D | MipsFastISel.cpp | 1118 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
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| D | MipsSEISelLowering.cpp | 3650 : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1); in emitFPROUND_PSEUDO()
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| /external/v8/src/mips/ |
| D | constants-mips.h | 586 MFC1 = ((0U << 3) + 0) << 21, enumerator
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| D | disasm-mips.cc | 1581 case MFC1: in DecodeTypeRegister()
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| D | assembler-mips.cc | 2611 GenInstrRegister(COP1, MFC1, rt, fs, f0); in mfc1()
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| D | simulator-mips.cc | 3670 case MFC1: in DecodeTypeRegisterCOP1()
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_common.c | 158 #define MFC1 (HI(17)) macro
1329 return push_inst(compiler, MFC1 | flags | T(dst) | FS(TMP_FREG1), MOVABLE_INS); in sljit_emit_fop1_conv_sw_from_f64()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 615 MFC1 = ((0U << 3) + 0) << 21, enumerator
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| D | disasm-mips64.cc | 1363 case MFC1: in DecodeTypeRegisterCOP1()
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| D | assembler-mips64.cc | 3003 GenInstrRegister(COP1, MFC1, rt, fs, f0); in mfc1()
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1055 16444U, // MFC1
2769 0U, // MFC1
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1810 UINT64_C(1140850688), // MFC1
5689 case Mips::MFC1:
9536 Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MFC1 = 1797
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