| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.h | 311 MFENCE, enumerator
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| D | X86InstrInfo.td | 113 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
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| D | X86GenAsmWriter.inc | 1231 4888U, // MFENCE
5962 "SDrr_Int\000MAXSSrm\000MAXSSrm_Int\000MAXSSrr\000MAXSSrr_Int\000MFENCE\000"
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| D | X86GenAsmWriter1.inc | 1231 3608U, // MFENCE
6705 "SDrr_Int\000MAXSSrm\000MAXSSrm_Int\000MAXSSrr\000MAXSSrr_Int\000MFENCE\000"
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| D | X86GenInstrInfo.inc | 1234 MFENCE = 1218,
5402 …0, 0, "MFENCE", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x15c000…
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| D | X86ISelLowering.cpp | 10202 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); in LowerMEMBARRIER()
10220 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); in LowerATOMIC_FENCE()
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| D | X86InstrSSE.td | 3196 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3201 def : Pat<(X86MFence), (MFENCE)>;
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| D | X86GenAsmMatcher.inc | 3811 { X86::MFENCE, "mfence", Convert, { }, 0},
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86SpeculativeLoadHardening.cpp | 387 if (MI.getOpcode() == X86::MFENCE) in hasVulnerableLoad()
1423 if (MI.getOpcode() == X86::MFENCE) in tracePredStateThroughBlocksAndHarden()
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| D | X86ISelLowering.h | 540 MFENCE, enumerator
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| D | X86SchedSkylakeClient.td | 824 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
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| D | X86SchedBroadwell.td | 667 MFENCE,
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| D | X86SchedHaswell.td | 1132 MFENCE,
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| D | X86SchedSkylakeServer.td | 891 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
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| D | X86InstrInfo.td | 133 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
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| D | X86InstrSSE.td | 3129 def MFENCE : I<0xAE, MRM_F0, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>,
3133 def : Pat<(X86MFence), (MFENCE)>;
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 517 MFENCE, enumerator
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| D | X86InstrInfo.td | 127 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
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| D | X86InstrSSE.td | 3688 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3693 def : Pat<(X86MFence), (MFENCE)>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | Atomics.rst | 436 fences generate an ``MFENCE``, other fences do not cause any code to be
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| /external/llvm/docs/ |
| D | Atomics.rst | 436 fences generate an ``MFENCE``, other fences do not cause any code to be
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 5521 {DBGFIELD("MFENCE") 1, false, false, 6, 2, 1, 1, 0, 0}, // #809
6737 {DBGFIELD("MFENCE") 2, false, false, 166, 2, 20, 1, 0, 0}, // #809
7953 {DBGFIELD("MFENCE") 1, false, false, 603, 2, 1, 1, 0, 0}, // #809
9169 {DBGFIELD("MFENCE") 3, false, false, 157, 3, 21, 1, 0, 0}, // #809
10385 {DBGFIELD("MFENCE") 1, false, false, 2955, 3, 1, 1, 0, 0}, // #809
11601 {DBGFIELD("MFENCE") 2, false, false, 166, 2, 20, 1, 0, 0}, // #809
12817 {DBGFIELD("MFENCE") 1, false, false, 1583, 1, 1, 1, 0, 0}, // #809
14033 {DBGFIELD("MFENCE") 3, false, false, 157, 3, 21, 1, 0, 0}, // #809
15249 {DBGFIELD("MFENCE") 1, false, false, 6, 1, 1, 1, 0, 0}, // #809
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| D | X86GenGlobalISel.inc | 9927 // (intrinsic_void 6429:{ *:[iPTR] }) => (MFENCE)
9928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MFENCE,
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| /external/capstone/arch/X86/ |
| D | X86GenAsmWriter.inc | 1375 14298U, // MFENCE
7646 0U, // MFENCE
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| D | X86GenAsmWriter1.inc | 1375 11414U, // MFENCE
7646 0U, // MFENCE
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