| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 420 MFLO = 1, enumerator
1024 return Latency::DIV + Latency::MFLO; in DivLatency()
1030 return 1 + Latency::DIV + Latency::MFLO; in DivLatency()
1040 return Latency::DIVU + Latency::MFLO; in DivuLatency()
1046 return 1 + Latency::DIVU + Latency::MFLO; in DivuLatency()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelDAGToDAG.cpp | 254 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, in Select()
290 unsigned Opc = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64); in Select()
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| D | MipsInstrInfo.cpp | 118 Opc = Mips::MFLO, SrcReg = 0; in copyPhysReg()
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| D | MipsInstrInfo.td | 759 def MFLO : MoveFromLOHI<0x12, "mflo">;
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| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 451 MFLO = 1, enumerator
501 latency = Latency::DMULT + Latency::MFLO; in DmulLatency()
569 latency = Latency::DDIV + Latency::MFLO; in DdivLatency()
582 latency = Latency::DDIVU + Latency::MFLO; in DdivuLatency()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 100 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; in copyPhysReg()
238 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); in storeRegToStack()
350 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; in expandPostRAPseudo()
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| D | MipsISelLowering.h | 78 MFLO, enumerator
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| D | MipsSEISelLowering.cpp | 445 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); in selectMADD()
517 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub); in selectMSUB()
1284 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult); in lowerMulDiv()
1304 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op); in extractLOHI()
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| D | MipsSEFrameLowering.cpp | 800 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
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| D | MipsFastISel.cpp | 1698 : Mips::MFLO; in selectDivRem()
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| D | MipsInstrInfo.td | 92 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
1977 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 466 return push_inst(compiler, MFLO | D(dst), DR(dst)); in emit_single_op()
469 return push_inst(compiler, MFLO | D(dst), DR(dst)); in emit_single_op()
474 FAIL_IF(push_inst(compiler, MFLO | D(dst), DR(dst))); in emit_single_op()
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| D | sljitNativeMIPS_32.c | 375 return push_inst(compiler, MFLO | D(dst), DR(dst)); in emit_single_op()
380 FAIL_IF(push_inst(compiler, MFLO | D(dst), DR(dst))); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 160 #define MFLO (HI(0) | LO(18)) macro
1083 FAIL_IF(push_inst(compiler, MFLO | D(SLJIT_R0), DR(SLJIT_R0))); in sljit_emit_op0()
1104 FAIL_IF(push_inst(compiler, MFLO | D(SLJIT_R0), DR(SLJIT_R0))); in sljit_emit_op0()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 105 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; in copyPhysReg()
311 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); in storeRegToStack()
428 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; in expandPostRAPseudo()
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| D | MipsISelLowering.h | 129 MFLO, enumerator
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| D | MipsSEFrameLowering.cpp | 823 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
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| D | MipsScheduleP5600.td | 169 def : InstRW<[P5600WriteAL2], (instrs CLO, CLZ, DI, EI, MFHI, MFLO,
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| D | MipsSEISelLowering.cpp | 1237 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult); in lowerMulDiv()
1257 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op); in extractLOHI()
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| D | MipsFastISel.cpp | 1924 : Mips::MFLO; in selectDivRem()
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| /external/v8/src/mips/ |
| D | constants-mips.h | 518 MFLO = ((2U << 3) + 2), enumerator
1286 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) |
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| D | disasm-mips.cc | 1348 case MFLO: in DecodeTypeRegisterSPECIAL()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 500 MFLO = ((2U << 3) + 2), enumerator
1328 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) |
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| D | disasm-mips64.cc | 1531 case MFLO: in DecodeTypeRegisterSPECIAL()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4015 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4064 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4102 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4726 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulImm()
4746 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
4768 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
4789 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulOU()
4817 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandDMULMacro()
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