| /external/llvm/test/MC/ARM/ |
| D | thumbv8m.s | 198 MRS r1, MSP_NS label
202 MRS r3, PRIMASK_NS label
206 MRS r5, SP_NS label
208 MRS r6,MSPLIM label
210 MRS r7,PSPLIM label
217 MRS r10, MSPLIM_NS label
223 MRS r12, BASEPRI_NS label
226 MRS r12, BASEPRI_MAX_NS label
|
| D | thumbv7m.s | 10 @ MRS
|
| D | thumb2-mclass.s | 10 @ MRS
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | thumbv8m.s | 198 MRS r1, MSP_NS label
202 MRS r3, PRIMASK_NS label
206 MRS r5, SP_NS label
208 MRS r6,MSPLIM label
210 MRS r7,PSPLIM label
217 MRS r10, MSPLIM_NS label
221 MRS r12, BASEPRI_NS label
229 MRS r8, 146 label
|
| D | thumbv7m.s | 10 @ MRS
|
| D | thumb2-mclass.s | 10 @ MRS
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | flags-multiuse.ll | 25 ; Currently, the comparison is emitted again. An MSR/MRS pair would also be
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | flags-multiuse.ll | 28 ; Currently, the comparison is emitted again. An MSR/MRS pair would also be
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | thumb2-mclass.s | 9 @ MRS
|
| /external/llvm/test/CodeGen/ARM/ |
| D | copy-cpsr.ll | 26 ; In Thumb mode v7M and v7AR have different MRS/MSR instructions that happen
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-MSR-MClass.txt | 4 # MRS
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | copy-cpsr.ll | 26 ; In Thumb mode v7M and v7AR have different MRS/MSR instructions that happen
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-MSR-MClass.txt | 4 # MRS
|
| D | invalid-thumbv7.txt | 384 # Undefined encodings for MSR/MRS (banked register)
|
| D | invalid-armv7.txt | 506 # Undefined encodings for MSR/MRS (banked register)
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64.td | 135 // Named operands for MRS/MSR/TLBI/...
|
| D | AArch64ISelDAGToDAG.cpp | 2433 AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other, in tryReadRegister()
2450 AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other, in tryReadRegister()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64.td | 233 // Named operands for MRS/MSR/TLBI/...
|
| D | AArch64ExpandPseudoInsts.cpp | 912 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg) in expandMI()
|
| D | AArch64ISelDAGToDAG.cpp | 2637 AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other, in tryReadRegister()
2654 AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other, in tryReadRegister()
|
| /external/capstone/bindings/ocaml/ |
| D | arm64_const.ml | 46 (* System registers for MRS *)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | arm64-system-encoding.s | 59 ; MSR/MRS instructions
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-system-encoding.s | 58 ; MSR/MRS instructions
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 343 def : InstRW<[R52WriteLd], (instregex "MRS", "MRSbanked")>;
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 742 MRS = SystemSysRegFixed | 0x00200000, enumerator
|