| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 408 MTC1 = 4, enumerator
643 return Latency::MTC1; in Mthc1Latency()
651 return Latency::MTC1 + 1; in MoveLatency()
679 return Latency::MTC1 + Mthc1Latency() + Latency::CVT_D_L; in CvtDUwLatency()
681 return Latency::BRANCH + Latency::MTC1 + 1 + Latency::MTC1 + in CvtDUwLatency()
736 return 1 + Latency::MTC1 + Mthc1Latency() + Latency::BRANCH + Latency::SUB_D + in Trunc_uw_dLatency()
742 return 1 + Latency::MTC1 + Latency::BRANCH + Latency::SUB_S + in Trunc_uw_sLatency()
757 return Latency::MTC1; in FmoveLowLatency()
759 return Latency::MFHC1 + Latency::MTC1 + Latency::MTHC1; in FmoveLowLatency()
827 return UlwLatency() + Latency::MTC1; in Ulwc1Latency()
[all …]
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| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 441 MTC1 = 4, enumerator
741 return UlwLatency() + Latency::MTC1; in Ulwc1Latency()
1014 Latency::MFC1 + 1 + XorLatency() + Latency::MTC1; in NegsLatency()
1046 Latency::MTC1; in Float32RoundLatency()
1114 3 * Latency::DMFC1 + OrLatency() + Latency::MTC1 + Latency::MOV_S + in TruncUlSLatency()
1488 return Latency::MTC1 + Latency::CVT_D_W; in GetInstructionLatency()
1490 return Latency::MTC1 + Latency::CVT_S_W; in GetInstructionLatency()
1529 Latency::MTC1 + Latency::MFC1 + Latency::MTHC1 + 1; in GetInstructionLatency()
1534 Latency::MTC1 + 2 * Latency::MFC1 + 2 + MovzLatency(); in GetInstructionLatency()
1546 return Latency::MFHC1 + Latency::MTC1 + Latency::MTHC1; in GetInstructionLatency()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 182 def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
363 def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
364 def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
366 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
367 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>;
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| D | MipsExpandPseudo.cpp | 90 const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1); in ExpandBuildPairF64()
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| D | MipsInstrInfo.cpp | 124 Opc = Mips::MTC1; in copyPhysReg()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 118 Opc = Mips::MTC1; in copyPhysReg()
369 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo()
372 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false); in expandPostRAPseudo()
378 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true); in expandPostRAPseudo()
652 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); in expandBuildPairF64()
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| D | MipsAsmPrinter.cpp | 777 if (Opcode == Mips::MTC1) { in EmitInstrRegReg()
816 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
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| D | MipsInstrFPU.td | 368 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
605 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
606 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
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| D | MipsFastISel.cpp | 350 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 123 Opc = Mips::MTC1; in copyPhysReg()
447 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo()
451 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); in expandPostRAPseudo()
458 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); in expandPostRAPseudo()
814 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); in expandBuildPairF64()
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| D | MipsAsmPrinter.cpp | 832 if (Opcode == Mips::MTC1) { in EmitInstrRegReg()
872 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
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| D | MipsInstrFPU.td | 494 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
863 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1;
864 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1;
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| D | MipsScheduleP5600.td | 543 def : InstRW<[P5600WriteMoveGPRToFPU], (instrs CTC1, MTC1, MTC1_D64, MTHC1_D32,
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| D | MipsFastISel.cpp | 395 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
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| D | MipsSEISelLowering.cpp | 3754 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1); in emitFPEXTEND_PSEUDO()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/MIR/Mips/ |
| D | live-debug-values-reg-copy.mir | 190 $f0 = MTC1 killed $v0, debug-location !19
226 $f0 = MTC1 killed $s0, debug-location !19
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_common.c | 162 #define MTC1 (HI(17) | (4 << 21)) macro
1352 FAIL_IF(push_inst(compiler, MTC1 | flags | T(src) | FS(TMP_FREG1), MOVABLE_INS)); in sljit_emit_fop1_conv_f64_from_sw()
1363 FAIL_IF(push_inst(compiler, MTC1 | flags | T(TMP_REG1) | FS(TMP_FREG1), MOVABLE_INS)); in sljit_emit_fop1_conv_f64_from_sw()
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| /external/v8/src/mips/ |
| D | constants-mips.h | 589 MTC1 = ((0U << 3) + 4) << 21, enumerator
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| D | disasm-mips.cc | 1587 case MTC1: in DecodeTypeRegister()
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| D | assembler-mips.cc | 2601 GenInstrRegister(COP1, MTC1, rt, fs, f0); in mtc1()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 619 MTC1 = ((0U << 3) + 4) << 21, enumerator
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| D | disasm-mips64.cc | 1372 case MTC1: in DecodeTypeRegisterCOP1()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | select-dbl.ll | 102 ; MM32R3: mtc1 $7, $f2 # <MCInst #{{.*}} MTC1
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1172 704599U, // MTC1
2886 0U, // MTC1
4534 // CTC1, CTC1_MM, DAHI, DATI, DMTC1, MTC1, MTC1_MM, MTHC1_MM, MTHI_DSP, M...
4585 // CTC1, CTC1_MM, DMTC1, MTC1, MTC1_MM, MTHC1_MM, MTHI_DSP, MTHLIP, MTLO_...
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3326 TOut.emitRR(Mips::MTC1, FirstReg, ATReg, IDLoc, STI); in expandLoadImmReal()
3422 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadImmReal()
3425 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), ATReg, IDLoc, STI); in expandLoadImmReal()
3426 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadImmReal()
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