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Searched refs:MULTU (Results 1 – 19 of 19) sorted by relevance

/external/v8/src/compiler/mips/
Dinstruction-scheduler-mips.cc304 MULTU = 4, enumerator
591 return latency + Latency::MULTU + 2; in MuluLatency()
984 return Latency::MULTU + Latency::MFHI; in MulhuLatency()
990 return 1 + Latency::MULTU + Latency::MFHI; in MulhuLatency()
/external/v8/src/compiler/mips64/
Dinstruction-scheduler-mips64.cc333 MULTU = 4, enumerator
527 latency = Latency::MULTU + Latency::MFHI; in MulhuLatency()
/external/v8/src/mips/
Dconstants-mips.h521 MULTU = ((3U << 3) + 1), enumerator
1287 FunctionFieldToBitNumber(MULT) | FunctionFieldToBitNumber(MULTU) |
Ddisasm-mips.cc1362 case MULTU: // @Mips32r6 == MUL_MUH_U. in DecodeTypeRegisterSPECIAL()
Dassembler-mips.cc1964 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU); in multu()
Dsimulator-mips.cc3903 case MULTU: in DecodeTypeRegisterSPECIAL()
/external/v8/src/mips64/
Dconstants-mips64.h509 MULTU = ((3U << 3) + 1), enumerator
1330 FunctionFieldToBitNumber(MULTU) | FunctionFieldToBitNumber(DMULTU) |
Ddisasm-mips64.cc1565 case MULTU: // @Mips64r6 == MUL_MUH_U. in DecodeTypeRegisterSPECIAL()
Dassembler-mips64.cc1970 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU); in multu()
Dsimulator-mips64.cc3861 case MULTU: in DecodeTypeRegisterSPECIAL()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.h146 MULTU, enumerator
DMipsDSPInstrInfo.td75 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
DMips16InstrInfo.td919 // Format: MULTU rx, ry MIPS16e
DMipsISelLowering.cpp186 case MipsISD::MULTU: return "MipsISD::MULTU"; in getTargetNodeName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.h198 MULTU, enumerator
DMipsDSPInstrInfo.td76 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
DMips16InstrInfo.td925 // Format: MULTU rx, ry MIPS16e
DMipsISelLowering.cpp268 case MipsISD::MULTU: return "MipsISD::MULTU"; in getTargetNodeName()
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_common.c165 #define MULTU (HI(0) | LO(25)) macro
1081 …FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? MULTU : MULT) | S(SLJIT_R0) | T(SLJIT_R1), MOVA… in sljit_emit_op0()