| /external/clang/test/Modules/Inputs/stress1/ |
| D | common.h | 8 namespace N01 { struct S00; }
44 namespace N01 {
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| /external/clang/test/Modules/ |
| D | stress1.cpp | 131 int f() { return N01::S00('a').method00('b') + (int)N00::S00(42) + function00(42) + g(); } in f()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1298 SDValue N01 = N0.getOperand(1); in combineShlAddConstant() local
1299 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); in combineShlAddConstant()
1306 N00.getOperand(0), N01), in combineShlAddConstant()
1307 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, in combineShlAddConstant()
1308 N00.getOperand(1), N01)); in combineShlAddConstant()
1394 SDValue N01 = N0.getOperand(1); in visitADD() local
1401 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); in visitADD()
2676 SDValue N01 = N0.getOperand(1); in MatchBSwapHWord() local
2687 SDValue N010 = N01.getOperand(0); in MatchBSwapHWord()
2690 SDValue N011 = N01.getOperand(1); in MatchBSwapHWord()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1712 SDValue N01 = N0.getOperand(1); in visitADD() local
1719 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11)); in visitADD()
3556 SDValue N01 = N0.getOperand(1); in MatchBSwapHWord() local
3560 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) { in MatchBSwapHWord()
3569 SDValue N010 = N01.getOperand(0); in MatchBSwapHWord()
3572 SDValue N011 = N01.getOperand(1); in MatchBSwapHWord()
3579 if (!isBSwapHWordElement(N01, Parts)) in MatchBSwapHWord()
4370 SDValue N01 = N->getOperand(0).getOperand(1); in distributeTruncateThroughAnd() local
4372 if (ConstantSDNode *N01C = isConstOrConstSplat(N01)) { in distributeTruncateThroughAnd()
4420 SDValue N01 = N0->getOperand(1); in visitSHL() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 2156 SDValue N01 = N0.getOperand(1); in visitADD() local
2163 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11)); in visitADD()
4892 SDValue N01 = N0.getOperand(1); in MatchBSwapHWord() local
4896 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) { in MatchBSwapHWord()
4901 if (!isBSwapHWordElement(N01, Parts)) in MatchBSwapHWord()
4913 if (!isBSwapHWordElement(N01, Parts)) in MatchBSwapHWord()
6218 SDValue N01 = N->getOperand(0).getOperand(1); in distributeTruncateThroughAnd() local
6219 if (isConstantOrConstantVector(N01, /* NoOpaques */ true)) { in distributeTruncateThroughAnd()
6224 SDValue Trunc01 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N01); in distributeTruncateThroughAnd()
6301 SDValue N01 = N0->getOperand(1); in visitSHL() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 34087 SDValue N01 = N0.getOperand(1); in combineShiftRightArithmetic() local
34088 APInt ShlConst = (cast<ConstantSDNode>(N01))->getAPIntValue(); in combineShiftRightArithmetic()
36804 SDValue N01 = N0.getOperand(1); in detectPMADDUBSW() local
36810 if (N01.getOpcode() == ISD::ZERO_EXTEND) in detectPMADDUBSW()
36811 std::swap(N00, N01); in detectPMADDUBSW()
36817 N01.getOpcode() != ISD::SIGN_EXTEND || in detectPMADDUBSW()
36824 N01 = N01.getOperand(0); in detectPMADDUBSW()
36830 N01.getValueType().getVectorElementType() != MVT::i8 || in detectPMADDUBSW()
36837 N01.getOpcode() != ISD::BUILD_VECTOR || in detectPMADDUBSW()
36853 SDValue N01Elt = N01.getOperand(i); in detectPMADDUBSW()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4686 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
4692 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
6608 SDValue N01 = N0->getOperand(1); in PerformVMULCombine() local
6611 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); in PerformVMULCombine()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 6701 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
6707 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
9131 SDValue N01 = N0->getOperand(1); in PerformVMULCombine() local
9134 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); in PerformVMULCombine()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 27768 SDValue N01 = N0.getOperand(1); in combineShiftRightAlgebraic() local
27769 APInt ShlConst = (cast<ConstantSDNode>(N01))->getAPIntValue(); in combineShiftRightAlgebraic()
27973 SDValue N01 = N0->getOperand(1); in combineANDXORWithAllOnesIntoANDNP() local
27975 N01 = peekThroughBitcasts(N01); in combineANDXORWithAllOnesIntoANDNP()
27979 if (!ISD::isBuildVectorAllOnes(N01.getNode())) { in combineANDXORWithAllOnesIntoANDNP()
27980 if (!VT.is256BitVector() || N01->getOpcode() != ISD::INSERT_SUBVECTOR) in combineANDXORWithAllOnesIntoANDNP()
27983 SDValue V1 = N01->getOperand(0); in combineANDXORWithAllOnesIntoANDNP()
27984 SDValue V2 = N01->getOperand(1); in combineANDXORWithAllOnesIntoANDNP()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 7535 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
7541 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
10590 SDValue N01 = N0->getOperand(1); in PerformVMULCombine() local
10593 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); in PerformVMULCombine()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2271 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
2277 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2613 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
2619 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
|