| /external/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 84 unsigned NumRegs = RC->getNumRegs(); in compute() local
87 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
116 RCI.NumRegs = N + CSRAlias.size(); in compute()
117 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
130 if (StressRA && RCI.NumRegs > StressRA) in compute()
131 RCI.NumRegs = StressRA; in compute()
136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
144 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
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| D | ExecutionDepsFix.cpp | 141 const unsigned NumRegs; member in __anon590fc3260311::ExeDepsFix
162 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} in ExeDepsFix()
273 assert(unsigned(rx) < NumRegs && "Invalid index"); in setLiveReg()
285 assert(unsigned(rx) < NumRegs && "Invalid index"); in kill()
296 assert(unsigned(rx) < NumRegs && "Invalid index"); in force()
328 for (unsigned rx = 0; rx != NumRegs; ++rx) in collapse()
351 for (unsigned rx = 0; rx != NumRegs; ++rx) { in merge()
373 LiveRegs = new LiveReg[NumRegs]; in enterBasicBlock()
376 for (unsigned rx = 0; rx != NumRegs; ++rx) { in enterBasicBlock()
405 for (unsigned rx = 0; rx != NumRegs; ++rx) { in enterBasicBlock()
[all …]
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| D | LiveVariables.cpp | 426 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) { in HandleRegMask() local
566 void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) { in runOnBlock() argument
617 for (unsigned i = 0; i != NumRegs; ++i) in runOnBlock()
627 const unsigned NumRegs = TRI->getNumRegs(); in runOnMachineFunction() local
628 PhysRegDef.assign(NumRegs, nullptr); in runOnMachineFunction()
629 PhysRegUse.assign(NumRegs, nullptr); in runOnMachineFunction()
649 runOnBlock(MBB, NumRegs); in runOnMachineFunction()
651 PhysRegDef.assign(NumRegs, nullptr); in runOnMachineFunction()
652 PhysRegUse.assign(NumRegs, nullptr); in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 96 unsigned NumRegs = RC->getNumRegs(); in compute() local
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
128 RCI.NumRegs = N + CSRAlias.size(); in compute()
129 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
142 if (StressRA && RCI.NumRegs > StressRA) in compute()
143 RCI.NumRegs = StressRA; in compute()
148 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
156 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
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| D | ExecutionDomainFix.cpp | 71 assert(unsigned(rx) < NumRegs && "Invalid index"); in setLiveReg()
82 assert(unsigned(rx) < NumRegs && "Invalid index"); in kill()
92 assert(unsigned(rx) < NumRegs && "Invalid index"); in force()
122 for (unsigned rx = 0; rx != NumRegs; ++rx) in collapse()
144 for (unsigned rx = 0; rx != NumRegs; ++rx) { in merge()
160 LiveRegs.assign(NumRegs, nullptr); in enterBasicBlock()
178 for (unsigned rx = 0; rx != NumRegs; ++rx) { in enterBasicBlock()
421 assert(NumRegs == RC->getNumRegs() && "Bad regclass"); in runOnMachineFunction()
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| D | LiveVariables.cpp | 426 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) { in HandleRegMask() local
566 void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) { in runOnBlock() argument
617 for (unsigned i = 0; i != NumRegs; ++i) in runOnBlock()
627 const unsigned NumRegs = TRI->getNumRegs(); in runOnMachineFunction() local
628 PhysRegDef.assign(NumRegs, nullptr); in runOnMachineFunction()
629 PhysRegUse.assign(NumRegs, nullptr); in runOnMachineFunction()
649 runOnBlock(MBB, NumRegs); in runOnMachineFunction()
651 PhysRegDef.assign(NumRegs, nullptr); in runOnMachineFunction()
652 PhysRegUse.assign(NumRegs, nullptr); in runOnMachineFunction()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 74 unsigned NumRegs = RC->getNumRegs(); in compute() local
77 RCI.Order.reset(new unsigned[NumRegs]); in compute()
96 RCI.NumRegs = N + CSRAlias.size(); in compute()
97 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
104 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
109 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
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| D | VirtRegMap.cpp | 93 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs(); in grow() local
94 Virt2PhysMap.resize(NumRegs); in grow()
95 Virt2StackSlotMap.resize(NumRegs); in grow()
96 Virt2ReMatIdMap.resize(NumRegs); in grow()
97 Virt2SplitMap.resize(NumRegs); in grow()
98 Virt2SplitKillMap.resize(NumRegs); in grow()
99 ReMatMap.resize(NumRegs); in grow()
100 ImplicitDefed.resize(NumRegs); in grow()
227 unsigned NumRegs = TRI->getNumRegs(); in FindUnusedRegisters() local
229 UnusedRegs.resize(NumRegs); in FindUnusedRegisters()
[all …]
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| D | RegisterClassInfo.h | 30 unsigned NumRegs; member
34 RCInfo() : Tag(0), NumRegs(0), ProperSubClass(false) {} in RCInfo()
36 return makeArrayRef(Order.get(), NumRegs);
81 return get(RC).NumRegs; in getNumAllocatableRegs()
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| D | RegAllocBase.h | 73 unsigned NumRegs; variable
76 LiveUnionArray(): NumRegs(0), Array(0) {} in LiveUnionArray()
79 unsigned numRegs() const { return NumRegs; } in numRegs()
86 assert(PhysReg < NumRegs && "physReg out of bounds");
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| D | ExecutionDepsFix.cpp | 116 const unsigned NumRegs; member in __anon1b4d15520211::ExeDepsFix
124 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} in ExeDepsFix()
186 assert(unsigned(rx) < NumRegs && "Invalid index"); in SetLiveReg()
188 LiveRegs = new DomainValue*[NumRegs]; in SetLiveReg()
189 std::fill(LiveRegs, LiveRegs+NumRegs, (DomainValue*)0); in SetLiveReg()
204 assert(unsigned(rx) < NumRegs && "Invalid index"); in Kill()
217 assert(unsigned(rx) < NumRegs && "Invalid index"); in Force()
249 for (unsigned rx = 0; rx != NumRegs; ++rx) in Collapse()
268 for (unsigned rx = 0; rx != NumRegs; ++rx) in Merge()
457 assert(NumRegs == RC->getNumRegs() && "Bad regclass"); in runOnMachineFunction()
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| D | RegAllocBasic.cpp | 223 NumRegs = NRegs; in init()
238 const unsigned NumRegs = TRI->getNumRegs(); in init() local
239 if (NumRegs != PhysReg2LiveUnion.numRegs()) { in init()
240 PhysReg2LiveUnion.init(UnionAllocator, NumRegs); in init()
249 for (unsigned r = 0; r != NumRegs; ++r) in clear()
252 NumRegs = 0; in clear()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 232 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { in getFirstUnallocated() argument
233 for (unsigned i = 0; i != NumRegs; ++i) in getFirstUnallocated()
236 return NumRegs; in getFirstUnallocated()
259 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { in AllocateReg() argument
260 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
261 if (FirstUnalloc == NumRegs) in AllocateReg()
272 unsigned NumRegs) { in AllocateReg() argument
273 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
274 if (FirstUnalloc == NumRegs) in AllocateReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/ |
| D | RegisterFile.cpp | 28 const llvm::MCRegisterInfo &mri, unsigned NumRegs) in RegisterFile() argument
31 initialize(SM, NumRegs);
34 void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) { in initialize() argument
39 addRegisterFile({} /* all registers */, NumRegs); in initialize()
293 unsigned NumRegs = NumPhysRegs[I]; in isAvailable() local
294 if (!NumRegs) in isAvailable()
304 if (RMT.NumPhysRegs < NumRegs) { in isAvailable()
313 if (RMT.NumPhysRegs < (RMT.NumUsedPhysRegs + NumRegs)) in isAvailable()
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| D | RegisterFile.h | 129 void initialize(const llvm::MCSchedModel &SM, unsigned NumRegs);
133 unsigned NumRegs = 0);
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 29 unsigned NumRegs; member
36 : Tag(0), NumRegs(0), ProperSubClass(false), MinCost(0), in RCInfo()
40 return makeArrayRef(Order.get(), NumRegs);
87 return get(RC).NumRegs; in getNumAllocatableRegs()
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| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 238 unsigned NumRegs; in printRegOperand() local
241 NumRegs = 1; in printRegOperand()
244 NumRegs = 1; in printRegOperand()
247 NumRegs = 2; in printRegOperand()
250 NumRegs = 2; in printRegOperand()
253 NumRegs = 4; in printRegOperand()
256 NumRegs = 4; in printRegOperand()
259 NumRegs = 3; in printRegOperand()
262 NumRegs = 8; in printRegOperand()
265 NumRegs = 8; in printRegOperand()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 34 unsigned NumRegs = 0; member
43 return makeArrayRef(Order.get(), NumRegs);
91 return get(RC).NumRegs; in getNumAllocatableRegs()
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCRegisterInfo.h | 141 unsigned NumRegs; // Number of entries in the array variable
157 NumRegs = NR; in InitMCRegisterInfo()
199 assert(RegNo < NumRegs &&
256 return NumRegs; in getNumRegs()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 64 unsigned Opc, bool IsExt, unsigned NumRegs);
107 unsigned char NumRegs; // D registers loaded or stored member
415 unsigned NumRegs = TableEntry->NumRegs; in ExpandVLD() local
427 if (NumRegs > 2) in ExpandVLD()
429 if (NumRegs > 3) in ExpandVLD()
479 unsigned NumRegs = TableEntry->NumRegs; in ExpandVST() local
499 if (NumRegs > 2) in ExpandVST()
501 if (NumRegs > 3) in ExpandVST()
527 unsigned NumRegs = TableEntry->NumRegs; in ExpandLaneOp() local
553 if (NumRegs > 1) in ExpandLaneOp()
[all …]
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 156 unsigned NumRegs; // Number of entries in the array variable
259 NumRegs = NR; in InitMCRegisterInfo()
329 assert(RegNo < NumRegs &&
374 return NumRegs; in getNumRegs()
428 assert(RegNo < NumRegs && in getEncodingValue()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 157 unsigned NumRegs; // Number of entries in the array variable
259 NumRegs = NR; in InitMCRegisterInfo()
339 assert(RegNo < NumRegs &&
384 return NumRegs; in getNumRegs()
450 assert(RegNo < NumRegs && in getEncodingValue()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyMachineFunctionInfo.cpp | 39 unsigned NumRegs = TLI.getNumRegisters(F.getContext(), VT); in ComputeLegalValueVTs() local
41 for (unsigned i = 0; i != NumRegs; ++i) in ComputeLegalValueVTs()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.cpp | 184 unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps; in EmitTargetCodeForMemcpy() local
187 DAG.getConstant(NumRegs, dl, MVT::i32)); in EmitTargetCodeForMemcpy()
191 DstPtrInfo = DstPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
192 SrcPtrInfo = SrcPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
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| /external/llvm/lib/Target/X86/ |
| D | X86CallingConv.h | 54 static const unsigned NumRegs = sizeof(RegList)/sizeof(RegList[0]); in CC_X86_32_MCUInReg() local
89 bool UseRegs = PendingMembers.size() <= std::min(2U, NumRegs - FirstFree); in CC_X86_32_MCUInReg()
|