| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | negative-immediates.s | 141 ORN r0, r1, #0xFFFFFF00
144 # CHECK-DISABLED: ORN
145 ORN r0, r1, #0xFEFFFEFF
148 # CHECK-DISABLED: ORN
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| D | negative-immediates-fail.s | 28 ORN r0, r1, #0xFFFFFF00 label
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| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-operand-const-t32.json | 48 "Orn", // ORN{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-t32.json | 45 "Orn", // ORN{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-t32.json | 45 "Orn", // ORN{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
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| D | cond-rd-rn-operand-rm-t32.json | 81 "Orn", // ORN{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 582 ORN = ORR | NOT, enumerator
618 ORN_w = LogicalShiftedFixed | ORN,
619 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits,
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| D | macro-assembler-arm64-inl.h | 73 LogicalMacro(rd, rn, operand, ORN); in Orn()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedThunderX2T99.td | 428 "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)",
450 "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)",
469 "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)",
1262 // ASIMD logical (MVN (alias for NOT), ORN, ORR)
1354 (instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|" #
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| D | AArch64SchedFalkorDetails.td | 661 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v8i8$")>;
725 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v16i8$")>;
900 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^ORN(W|X)r(r|s)$")>;
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| D | AArch64SchedExynosM3.td | 501 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)[WX]r[sx]$")>;
603 def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
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| D | AArch64InstrAtomics.td | 424 defm : LDOPregister_patterns_mod<"LDCLR", "atomic_load_and", "ORN">;
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| D | AArch64SchedCyclone.td | 412 // AND,BIC,CMTST,EOR,ORN,ORR
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| D | AArch64SchedExynosM1.td | 534 def : InstRW<[M1WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
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| D | AArch64SchedKryoDetails.td | 436 …(instregex "((AND|ORN|EOR|EON)S?(Wr[rsi]|v8i8|v4i16|v2i32)|(ORR|BIC)S?(Wr[rs]|v8i8|v4i16|v2i32))")…
442 …(instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))…
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/ |
| D | GlobalISelEmitter.td | 746 // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORN:{ *:[i32] } R0…
747 // NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ORN,
757 def ORN : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
758 def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 547 ORN = ORR | NOT, enumerator
583 ORN_w = LogicalShiftedFixed | ORN,
584 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedM1.td | 286 def : InstRW<[M1WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
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| D | AArch64SchedCyclone.td | 410 // AND,BIC,CMTST,EOR,ORN,ORR
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| D | AArch64SchedVulcan.td | 484 // ASIMD logical (MOV, MVN, ORN, ORR)
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| D | AArch64SchedKryoDetails.td | 436 …(instregex "((AND|ORN|EOR|EON)S?(Wr[rsi]|v8i8|v4i16|v2i32)|(ORR|BIC)S?(Wr[rs]|v8i8|v4i16|v2i32))")…
442 …(instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))…
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_64.c | 109 #define ORN 0xaa200000 macro
739 FAIL_IF(push_inst(compiler, (ORN ^ inv_bits) | RD(dst) | RN(TMP_ZERO) | RM(arg2))); in emit_op_imm()
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| D | sljitNativeSPARC_common.c | 162 #define ORN (OPC1(0x2) | OPC3(0x06)) macro
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 131 // AND,BIC,EOR,ORN,ORR
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 128 // AND,BIC,EOR,ORN,ORR
|