1//=- ARMScheduleSwift.td - Swift Scheduling Definitions -*- tablegen -*----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the itinerary class data for the Swift processor.. 11// 12//===----------------------------------------------------------------------===// 13 14// ===---------------------------------------------------------------------===// 15// This section contains legacy support for itineraries. This is 16// required until SD and PostRA schedulers are replaced by MachineScheduler. 17 18def SW_DIS0 : FuncUnit; 19def SW_DIS1 : FuncUnit; 20def SW_DIS2 : FuncUnit; 21 22def SW_ALU0 : FuncUnit; 23def SW_ALU1 : FuncUnit; 24def SW_LS : FuncUnit; 25def SW_IDIV : FuncUnit; 26def SW_FDIV : FuncUnit; 27 28// FIXME: Need bypasses. 29// FIXME: Model the multiple stages of IIC_iMOVix2, IIC_iMOVix2addpc, and 30// IIC_iMOVix2ld better. 31// FIXME: Model the special immediate shifts that are not microcoded. 32// FIXME: Do we need to model the fact that uses of r15 in a micro-op force it 33// to issue on pipe 1? 34// FIXME: Model the pipelined behavior of CMP / TST instructions. 35// FIXME: Better model the microcode stages of multiply instructions, especially 36// conditional variants. 37// FIXME: Add preload instruction when it is documented. 38// FIXME: Model non-pipelined nature of FP div / sqrt unit. 39 40// Swift machine model for scheduling and other instruction cost heuristics. 41def SwiftModel : SchedMachineModel { 42 let IssueWidth = 3; // 3 micro-ops are dispatched per cycle. 43 let MicroOpBufferSize = 45; // Based on NEON renamed registers. 44 let LoadLatency = 3; 45 let MispredictPenalty = 14; // A branch direction mispredict. 46 let CompleteModel = 0; // FIXME: Remove if all instructions are covered. 47 48 // FIXME: Remove when all errors have been fixed. 49 let FullInstRWOverlapCheck = 0; 50} 51 52// Swift predicates. 53def IsFastImmShiftSwiftPred : SchedPredicate<[{TII->isSwiftFastImmShift(MI)}]>; 54 55// Swift resource mapping. 56let SchedModel = SwiftModel in { 57 // Processor resources. 58 def SwiftUnitP01 : ProcResource<2>; // ALU unit. 59 def SwiftUnitP0 : ProcResource<1> { let Super = SwiftUnitP01; } // Mul unit. 60 def SwiftUnitP1 : ProcResource<1> { let Super = SwiftUnitP01; } // Br unit. 61 def SwiftUnitP2 : ProcResource<1>; // LS unit. 62 def SwiftUnitDiv : ProcResource<1>; 63 64 // Generic resource requirements. 65 def SwiftWriteP0OneCycle : SchedWriteRes<[SwiftUnitP0]>; 66 def SwiftWriteP0TwoCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 2; } 67 def SwiftWriteP0FourCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 4; } 68 def SwiftWriteP0SixCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 6; } 69 def SwiftWriteP0P1FourCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP1]> { 70 let Latency = 4; 71 } 72 def SwiftWriteP0P1SixCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP1]> { 73 let Latency = 6; 74 } 75 def SwiftWriteP01OneCycle : SchedWriteRes<[SwiftUnitP01]>; 76 def SwiftWriteP1TwoCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 2; } 77 def SwiftWriteP1FourCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 4; } 78 def SwiftWriteP1SixCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 6; } 79 def SwiftWriteP1EightCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 8; } 80 def SwiftWriteP1TwelveCyc : SchedWriteRes<[SwiftUnitP1]> { let Latency = 12; } 81 def SwiftWriteP01OneCycle2x : WriteSequence<[SwiftWriteP01OneCycle], 2>; 82 def SwiftWriteP01OneCycle3x : WriteSequence<[SwiftWriteP01OneCycle], 3>; 83 def SwiftWriteP01TwoCycle : SchedWriteRes<[SwiftUnitP01]> { let Latency = 2; } 84 def SwiftWriteP01ThreeCycleTwoUops : SchedWriteRes<[SwiftUnitP01, 85 SwiftUnitP01]> { 86 let Latency = 3; 87 let NumMicroOps = 2; 88 } 89 def SwiftWriteP0ThreeCycleThreeUops : SchedWriteRes<[SwiftUnitP0]> { 90 let Latency = 3; 91 let NumMicroOps = 3; 92 let ResourceCycles = [3]; 93 } 94 // Plain load without writeback. 95 def SwiftWriteP2ThreeCycle : SchedWriteRes<[SwiftUnitP2]> { 96 let Latency = 3; 97 } 98 def SwiftWriteP2FourCycle : SchedWriteRes<[SwiftUnitP2]> { 99 let Latency = 4; 100 } 101 // A store does not write to a register. 102 def SwiftWriteP2 : SchedWriteRes<[SwiftUnitP2]> { 103 let Latency = 0; 104 } 105 foreach Num = 1-4 in { 106 def SwiftWrite#Num#xP2 : WriteSequence<[SwiftWriteP2], Num>; 107 } 108 def SwiftWriteP01OneCycle2x_load : WriteSequence<[SwiftWriteP01OneCycle, 109 SwiftWriteP01OneCycle, 110 SwiftWriteP2ThreeCycle]>; 111 // 4.2.4 Arithmetic and Logical. 112 // ALU operation register shifted by immediate variant. 113 def SwiftWriteALUsi : SchedWriteVariant<[ 114 // lsl #2, lsl #1, or lsr #1. 115 SchedVar<IsFastImmShiftSwiftPred, [SwiftWriteP01TwoCycle]>, 116 SchedVar<NoSchedPred, [WriteALU]> 117 ]>; 118 def SwiftWriteALUsr : SchedWriteVariant<[ 119 SchedVar<IsPredicatedPred, [SwiftWriteP01ThreeCycleTwoUops]>, 120 SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]> 121 ]>; 122 def SwiftWriteALUSsr : SchedWriteVariant<[ 123 SchedVar<IsPredicatedPred, [SwiftWriteP0ThreeCycleThreeUops]>, 124 SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]> 125 ]>; 126 def SwiftReadAdvanceALUsr : SchedReadVariant<[ 127 SchedVar<IsPredicatedPred, [SchedReadAdvance<2>]>, 128 SchedVar<NoSchedPred, [NoReadAdvance]> 129 ]>; 130 // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR 131 // AND,BIC,EOR,ORN,ORR 132 // CLZ,RBIT,REV,REV16,REVSH,PKH 133 def : WriteRes<WriteALU, [SwiftUnitP01]>; 134 def : SchedAlias<WriteALUsi, SwiftWriteALUsi>; 135 def : SchedAlias<WriteALUsr, SwiftWriteALUsr>; 136 def : SchedAlias<WriteALUSsr, SwiftWriteALUSsr>; 137 def : ReadAdvance<ReadALU, 0>; 138 def : SchedAlias<ReadALUsr, SwiftReadAdvanceALUsr>; 139 def : SchedAlias<WriteLd, SwiftWriteP2ThreeCycle>; 140 def : SchedAlias<WriteST, SwiftWriteP2>; 141 142 143 def SwiftChooseShiftKindP01OneOrTwoCycle : SchedWriteVariant<[ 144 SchedVar<IsFastImmShiftSwiftPred, [SwiftWriteP01OneCycle]>, 145 SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]> 146 ]>; 147 148 // 4.2.5 Integer comparison 149 def : WriteRes<WriteCMP, [SwiftUnitP01]>; 150 def : SchedAlias<WriteCMPsi, SwiftChooseShiftKindP01OneOrTwoCycle>; 151 def : SchedAlias<WriteCMPsr, SwiftWriteP01TwoCycle>; 152 153 // 4.2.6 Shift, Move 154 // Shift 155 // ASR,LSL,ROR,RRX 156 // MOV(register-shiftedregister) MVN(register-shiftedregister) 157 // Move 158 // MOV,MVN 159 // MOVT 160 // Sign/Zero extension 161 def : InstRW<[SwiftWriteP01OneCycle], 162 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16", 163 "t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH", 164 "t2UXTB16")>; 165 // Pseudo instructions. 166 def : InstRW<[SwiftWriteP01OneCycle2x], 167 (instregex "MOVCCi32imm", "MOVi32imm", "t2MOVCCi32imm", 168 "t2MOVi32imm")>; 169 def : InstRW<[SwiftWriteP01OneCycle3x], 170 (instregex "MOV_ga_pcrel", "t2MOV_ga_pcrel", "t2MOVi16_ga_pcrel")>; 171 def : InstRW<[SwiftWriteP01OneCycle2x_load], 172 (instregex "MOV_ga_pcrel_ldr")>; 173 174 def SwiftWriteP0TwoCycleTwoUops : WriteSequence<[SwiftWriteP0OneCycle], 2>; 175 176 def SwiftPredP0OneOrTwoCycle : SchedWriteVariant<[ 177 SchedVar<IsPredicatedPred, [ SwiftWriteP0TwoCycleTwoUops ]>, 178 SchedVar<NoSchedPred, [ SwiftWriteP0OneCycle ]> 179 ]>; 180 181 // 4.2.7 Select 182 // SEL 183 def : InstRW<[SwiftPredP0OneOrTwoCycle], (instregex "SEL", "t2SEL")>; 184 185 // 4.2.8 Bitfield 186 // BFI,BFC, SBFX,UBFX 187 def : InstRW< [SwiftWriteP01TwoCycle], 188 (instregex "BFC", "BFI", "UBFX", "SBFX", "(t|t2)BFC", "(t|t2)BFI", 189 "(t|t2)UBFX", "(t|t2)SBFX")>; 190 191 // 4.2.9 Saturating arithmetic 192 def : InstRW< [SwiftWriteP01TwoCycle], 193 (instregex "QADD", "QSUB", "QDADD", "QDSUB", "SSAT", "SSAT16", "USAT", 194 "USAT16", "QADD8", "QADD16", "QSUB8", "QSUB16", "QASX", "QSAX", 195 "UQADD8", "UQADD16","UQSUB8","UQSUB16","UQASX","UQSAX", "t2QADD", 196 "t2QSUB", "t2QDADD", "t2QDSUB", "t2SSAT", "t2SSAT16", "t2USAT", 197 "t2QADD8", "t2QADD16", "t2QSUB8", "t2QSUB16", "t2QASX", "t2QSAX", 198 "t2UQADD8", "t2UQADD16","t2UQSUB8","t2UQSUB16","t2UQASX","t2UQSAX")>; 199 200 // 4.2.10 Parallel Arithmetic 201 // Not flag setting. 202 def : InstRW< [SwiftWriteALUsr], 203 (instregex "SADD8", "SADD16", "SSUB8", "SSUB16", "SASX", "SSAX", 204 "UADD8", "UADD16", "USUB8", "USUB16", "UASX", "USAX", "t2SADD8", 205 "t2SADD16", "t2SSUB8", "t2SSUB16", "t2SASX", "t2SSAX", "t2UADD8", 206 "t2UADD16", "t2USUB8", "t2USUB16", "t2UASX", "t2USAX")>; 207 // Flag setting. 208 def : InstRW< [SwiftWriteP01TwoCycle], 209 (instregex "SHADD8", "SHADD16", "SHSUB8", "SHSUB16", "SHASX", "SHSAX", 210 "SXTAB", "SXTAB16", "SXTAH", "UHADD8", "UHADD16", "UHSUB8", "UHSUB16", 211 "UHASX", "UHSAX", "UXTAB", "UXTAB16", "UXTAH", "t2SHADD8", "t2SHADD16", 212 "t2SHSUB8", "t2SHSUB16", "t2SHASX", "t2SHSAX", "t2SXTAB", "t2SXTAB16", 213 "t2SXTAH", "t2UHADD8", "t2UHADD16", "t2UHSUB8", "t2UHSUB16", "t2UHASX", 214 "t2UHSAX", "t2UXTAB", "t2UXTAB16", "t2UXTAH")>; 215 216 // 4.2.11 Sum of Absolute Difference 217 def : InstRW< [SwiftWriteP0P1FourCycle], (instregex "USAD8") >; 218 def : InstRW<[SwiftWriteP0P1FourCycle, ReadALU, ReadALU, SchedReadAdvance<2>], 219 (instregex "USADA8")>; 220 221 // 4.2.12 Integer Multiply (32-bit result) 222 // Two sources. 223 def : InstRW< [SwiftWriteP0FourCycle], 224 (instregex "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT", 225 "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDX", "t2MUL", 226 "t2SMMUL", "t2SMMULR", "t2SMULBB", "t2SMULBT", "t2SMULTB", "t2SMULTT", 227 "t2SMULWB", "t2SMULWT", "t2SMUSD")>; 228 229 def SwiftWriteP0P01FiveCycleTwoUops : 230 SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> { 231 let Latency = 5; 232 } 233 234 def SwiftPredP0P01FourFiveCycle : SchedWriteVariant<[ 235 SchedVar<IsPredicatedPred, [ SwiftWriteP0P01FiveCycleTwoUops ]>, 236 SchedVar<NoSchedPred, [ SwiftWriteP0FourCycle ]> 237 ]>; 238 239 def SwiftReadAdvanceFourCyclesPred : SchedReadVariant<[ 240 SchedVar<IsPredicatedPred, [SchedReadAdvance<4>]>, 241 SchedVar<NoSchedPred, [ReadALU]> 242 ]>; 243 244 // Multiply accumulate, three sources 245 def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU, 246 SwiftReadAdvanceFourCyclesPred], 247 (instregex "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR", 248 "t2MLA", "t2MLS", "t2SMMLA", "t2SMMLAR", "t2SMMLS", 249 "t2SMMLSR")>; 250 251 // 4.2.13 Integer Multiply (32-bit result, Q flag) 252 def : InstRW< [SwiftWriteP0FourCycle], 253 (instregex "SMUAD", "SMUADX", "t2SMUAD", "t2SMUADX")>; 254 def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU, 255 SwiftReadAdvanceFourCyclesPred], 256 (instregex "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLSD", "SMLSDX", 257 "SMLAWB", "SMLAWT", "t2SMLABB", "t2SMLABT", "t2SMLATB", "t2SMLATT", 258 "t2SMLSD", "t2SMLSDX", "t2SMLAWB", "t2SMLAWT")>; 259 def : InstRW< [SwiftPredP0P01FourFiveCycle], 260 (instregex "SMLAD", "SMLADX", "t2SMLAD", "t2SMLADX")>; 261 262 def SwiftP0P0P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> { 263 let Latency = 5; 264 let NumMicroOps = 3; 265 let ResourceCycles = [2, 1]; 266 } 267 def SwiftWrite1Cycle : SchedWriteRes<[]> { 268 let Latency = 1; 269 let NumMicroOps = 0; 270 } 271 def SwiftWrite5Cycle : SchedWriteRes<[]> { 272 let Latency = 5; 273 let NumMicroOps = 0; 274 } 275 def SwiftWrite6Cycle : SchedWriteRes<[]> { 276 let Latency = 6; 277 let NumMicroOps = 0; 278 } 279 280 // 4.2.14 Integer Multiply, Long 281 def : InstRW< [SwiftP0P0P01FiveCycle, SwiftWrite5Cycle], 282 (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$")>; 283 284 def Swift2P03P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> { 285 let Latency = 7; 286 let NumMicroOps = 5; 287 let ResourceCycles = [2, 3]; 288 } 289 290 // Aliasing sub-target specific WriteRes to generic ones 291 def : SchedAlias<WriteMUL16, SwiftWriteP0FourCycle>; 292 def : SchedAlias<WriteMUL32, SwiftWriteP0FourCycle>; 293 def : SchedAlias<WriteMUL64Lo, SwiftP0P0P01FiveCycle>; 294 def : SchedAlias<WriteMUL64Hi, SwiftWrite5Cycle>; 295 def : SchedAlias<WriteMAC16, SwiftPredP0P01FourFiveCycle>; 296 def : SchedAlias<WriteMAC32, SwiftPredP0P01FourFiveCycle>; 297 def : SchedAlias<WriteMAC64Lo, SwiftWrite5Cycle>; 298 def : SchedAlias<WriteMAC64Hi, Swift2P03P01FiveCycle>; 299 def : ReadAdvance<ReadMUL, 0>; 300 def : SchedAlias<ReadMAC, SwiftReadAdvanceFourCyclesPred>; 301 302 // 4.2.15 Integer Multiply Accumulate, Long 303 // 4.2.16 Integer Multiply Accumulate, Dual 304 // 4.2.17 Integer Multiply Accumulate Accumulate, Long 305 // We are being a bit inaccurate here. 306 def : InstRW< [SwiftWrite5Cycle, Swift2P03P01FiveCycle, ReadALU, ReadALU, 307 SchedReadAdvance<4>, SchedReadAdvance<3>], 308 (instregex "SMLAL", "UMLAL", "SMLALBT", 309 "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX", 310 "UMAAL", "t2SMLAL", "t2UMLAL", "t2SMLALBB", "t2SMLALBT", 311 "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX", "t2SMLSLD", "t2SMLSLDX", 312 "t2UMAAL")>; 313 314 def SwiftDiv : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> { 315 let NumMicroOps = 1; 316 let Latency = 14; 317 let ResourceCycles = [1, 14]; 318 } 319 // 4.2.18 Integer Divide 320 def : WriteRes<WriteDIV, [SwiftUnitDiv]>; // Workaround. 321 def : InstRW <[SwiftDiv], 322 (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>; 323 324 // 4.2.19 Integer Load Single Element 325 // 4.2.20 Integer Load Signextended 326 def SwiftWriteP2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> { 327 let Latency = 3; 328 let NumMicroOps = 2; 329 } 330 def SwiftWriteP2P01FourCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> { 331 let Latency = 4; 332 let NumMicroOps = 2; 333 } 334 def SwiftWriteP2P01P01FourCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01, 335 SwiftUnitP01]> { 336 let Latency = 4; 337 let NumMicroOps = 3; 338 } 339 def SwiftWriteP2P2ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2]> { 340 let Latency = 3; 341 let NumMicroOps = 2; 342 } 343 def SwiftWriteP2P2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2, 344 SwiftUnitP01]> { 345 let Latency = 3; 346 let NumMicroOps = 3; 347 } 348 def SwiftWrBackOne : SchedWriteRes<[]> { 349 let Latency = 1; 350 let NumMicroOps = 0; 351 } 352 def SwiftWriteLdFour : SchedWriteRes<[]> { 353 let Latency = 4; 354 let NumMicroOps = 0; 355 } 356 // Not accurate. 357 def : InstRW<[SwiftWriteP2ThreeCycle], 358 (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)", 359 "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)", 360 "tLDR(r|i|spi|pci|pciASM)")>; 361 def : InstRW<[SwiftWriteP2ThreeCycle], 362 (instregex "LDRH$", "PICLDR$", "PICLDR(H|B)$", "LDRcp$")>; 363 def : InstRW<[SwiftWriteP2P01FourCycle], 364 (instregex "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$", 365 "t2LDRpci_pic", "tLDRS(B|H)")>; 366 def : InstRW<[SwiftWriteP2P01ThreeCycle, SwiftWrBackOne], 367 (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)", 368 "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)", 369 "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T")>; 370 def : InstRW<[SwiftWriteP2P01P01FourCycle, SwiftWrBackOne], 371 (instregex "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)", 372 "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)?")>; 373 374 // 4.2.21 Integer Dual Load 375 // Not accurate. 376 def : InstRW<[SwiftWriteP2P2ThreeCycle, SwiftWriteLdFour], 377 (instregex "t2LDRDi8", "LDRD$")>; 378 def : InstRW<[SwiftWriteP2P2P01ThreeCycle, SwiftWriteLdFour, SwiftWrBackOne], 379 (instregex "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)")>; 380 381 // 4.2.22 Integer Load, Multiple 382 // NumReg = 1 .. 16 383 foreach Lat = 3-25 in { 384 def SwiftWriteLM#Lat#Cy : SchedWriteRes<[SwiftUnitP2]> { 385 let Latency = Lat; 386 } 387 def SwiftWriteLM#Lat#CyNo : SchedWriteRes<[]> { 388 let Latency = Lat; 389 let NumMicroOps = 0; 390 } 391 } 392 // Predicate. 393 foreach NumAddr = 1-16 in { 394 def SwiftLMAddr#NumAddr#Pred : SchedPredicate<"TII->getNumLDMAddresses(*MI) == "#NumAddr>; 395 } 396 def SwiftWriteLDMAddrNoWB : SchedWriteRes<[SwiftUnitP01]> { let Latency = 0; } 397 def SwiftWriteLDMAddrWB : SchedWriteRes<[SwiftUnitP01, SwiftUnitP01]>; 398 def SwiftWriteLM : SchedWriteVariant<[ 399 SchedVar<SwiftLMAddr2Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy]>, 400 SchedVar<SwiftLMAddr3Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 401 SwiftWriteLM5Cy]>, 402 SchedVar<SwiftLMAddr4Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 403 SwiftWriteLM5Cy, SwiftWriteLM6Cy]>, 404 SchedVar<SwiftLMAddr5Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 405 SwiftWriteLM5Cy, SwiftWriteLM6Cy, 406 SwiftWriteLM7Cy]>, 407 SchedVar<SwiftLMAddr6Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 408 SwiftWriteLM5Cy, SwiftWriteLM6Cy, 409 SwiftWriteLM7Cy, SwiftWriteLM8Cy]>, 410 SchedVar<SwiftLMAddr7Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 411 SwiftWriteLM5Cy, SwiftWriteLM6Cy, 412 SwiftWriteLM7Cy, SwiftWriteLM8Cy, 413 SwiftWriteLM9Cy]>, 414 SchedVar<SwiftLMAddr8Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 415 SwiftWriteLM5Cy, SwiftWriteLM6Cy, 416 SwiftWriteLM7Cy, SwiftWriteLM8Cy, 417 SwiftWriteLM9Cy, SwiftWriteLM10Cy]>, 418 SchedVar<SwiftLMAddr9Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 419 SwiftWriteLM5Cy, SwiftWriteLM6Cy, 420 SwiftWriteLM7Cy, SwiftWriteLM8Cy, 421 SwiftWriteLM9Cy, SwiftWriteLM10Cy, 422 SwiftWriteLM11Cy]>, 423 SchedVar<SwiftLMAddr10Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 424 SwiftWriteLM5Cy, SwiftWriteLM6Cy, 425 SwiftWriteLM7Cy, SwiftWriteLM8Cy, 426 SwiftWriteLM9Cy, SwiftWriteLM10Cy, 427 SwiftWriteLM11Cy, SwiftWriteLM12Cy]>, 428 SchedVar<SwiftLMAddr11Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 429 SwiftWriteLM5Cy, SwiftWriteLM6Cy, 430 SwiftWriteLM7Cy, SwiftWriteLM8Cy, 431 SwiftWriteLM9Cy, SwiftWriteLM10Cy, 432 SwiftWriteLM11Cy, SwiftWriteLM12Cy, 433 SwiftWriteLM13Cy]>, 434 SchedVar<SwiftLMAddr12Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 435 SwiftWriteLM5Cy, SwiftWriteLM6Cy, 436 SwiftWriteLM7Cy, SwiftWriteLM8Cy, 437 SwiftWriteLM9Cy, SwiftWriteLM10Cy, 438 SwiftWriteLM11Cy, SwiftWriteLM12Cy, 439 SwiftWriteLM13Cy, SwiftWriteLM14Cy]>, 440 SchedVar<SwiftLMAddr13Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 441 SwiftWriteLM5Cy, SwiftWriteLM6Cy, 442 SwiftWriteLM7Cy, SwiftWriteLM8Cy, 443 SwiftWriteLM9Cy, SwiftWriteLM10Cy, 444 SwiftWriteLM11Cy, SwiftWriteLM12Cy, 445 SwiftWriteLM13Cy, SwiftWriteLM14Cy, 446 SwiftWriteLM15Cy]>, 447 SchedVar<SwiftLMAddr14Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 448 SwiftWriteLM5Cy, SwiftWriteLM6Cy, 449 SwiftWriteLM7Cy, SwiftWriteLM8Cy, 450 SwiftWriteLM9Cy, SwiftWriteLM10Cy, 451 SwiftWriteLM11Cy, SwiftWriteLM12Cy, 452 SwiftWriteLM13Cy, SwiftWriteLM14Cy, 453 SwiftWriteLM15Cy, SwiftWriteLM16Cy]>, 454 SchedVar<SwiftLMAddr15Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 455 SwiftWriteLM5Cy, SwiftWriteLM6Cy, 456 SwiftWriteLM7Cy, SwiftWriteLM8Cy, 457 SwiftWriteLM9Cy, SwiftWriteLM10Cy, 458 SwiftWriteLM11Cy, SwiftWriteLM12Cy, 459 SwiftWriteLM13Cy, SwiftWriteLM14Cy, 460 SwiftWriteLM15Cy, SwiftWriteLM16Cy, 461 SwiftWriteLM17Cy]>, 462 SchedVar<SwiftLMAddr16Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 463 SwiftWriteLM5Cy, SwiftWriteLM6Cy, 464 SwiftWriteLM7Cy, SwiftWriteLM8Cy, 465 SwiftWriteLM9Cy, SwiftWriteLM10Cy, 466 SwiftWriteLM11Cy, SwiftWriteLM12Cy, 467 SwiftWriteLM13Cy, SwiftWriteLM14Cy, 468 SwiftWriteLM15Cy, SwiftWriteLM16Cy, 469 SwiftWriteLM17Cy, SwiftWriteLM18Cy]>, 470 // Unknow number of registers, just use resources for two registers. 471 SchedVar<NoSchedPred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 472 SwiftWriteLM5CyNo, SwiftWriteLM6CyNo, 473 SwiftWriteLM7CyNo, SwiftWriteLM8CyNo, 474 SwiftWriteLM9CyNo, SwiftWriteLM10CyNo, 475 SwiftWriteLM11CyNo, SwiftWriteLM12CyNo, 476 SwiftWriteLM13CyNo, SwiftWriteLM14CyNo, 477 SwiftWriteLM15CyNo, SwiftWriteLM16CyNo, 478 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo]> 479 480 ]> { let Variadic=1; } 481 482 def : InstRW<[SwiftWriteLM, SwiftWriteLDMAddrNoWB], 483 (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$", 484 "(t|sys)LDM(IA|DA|DB|IB)$")>; 485 def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM], 486 (instregex /*"t2LDMIA_RET", "tLDMIA_RET", "LDMIA_RET",*/ 487 "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>; 488 def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM, SwiftWriteP1TwoCycle], 489 (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "tPOP")>; 490 // 4.2.23 Integer Store, Single Element 491 def : InstRW<[SwiftWriteP2], 492 (instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX", 493 "t2STR(i12|i8|s)$", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>; 494 495 def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteP2], 496 (instregex "STR(B_|_|BT_|T_)(PRE_IMM|PRE_REG|POST_REG|POST_IMM)", 497 "STR(i|r)_preidx", "STRB(i|r)_preidx", "STRH_preidx", "STR(H_|HT_)(PRE|POST)", 498 "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)", 499 "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>; 500 501 // 4.2.24 Integer Store, Dual 502 def : InstRW<[SwiftWriteP2, SwiftWriteP2, SwiftWriteP01OneCycle], 503 (instregex "STRD$", "t2STRDi8")>; 504 def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteP2, SwiftWriteP2, 505 SwiftWriteP01OneCycle], 506 (instregex "(t2|t)STRD_(POST|PRE)", "STRD_(POST|PRE)")>; 507 508 // 4.2.25 Integer Store, Multiple 509 def SwiftWriteStIncAddr : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> { 510 let Latency = 0; 511 let NumMicroOps = 2; 512 } 513 foreach NumAddr = 1-16 in { 514 def SwiftWriteSTM#NumAddr : WriteSequence<[SwiftWriteStIncAddr], NumAddr>; 515 } 516 def SwiftWriteSTM : SchedWriteVariant<[ 517 SchedVar<SwiftLMAddr2Pred, [SwiftWriteSTM2]>, 518 SchedVar<SwiftLMAddr3Pred, [SwiftWriteSTM3]>, 519 SchedVar<SwiftLMAddr4Pred, [SwiftWriteSTM4]>, 520 SchedVar<SwiftLMAddr5Pred, [SwiftWriteSTM5]>, 521 SchedVar<SwiftLMAddr6Pred, [SwiftWriteSTM6]>, 522 SchedVar<SwiftLMAddr7Pred, [SwiftWriteSTM7]>, 523 SchedVar<SwiftLMAddr8Pred, [SwiftWriteSTM8]>, 524 SchedVar<SwiftLMAddr9Pred, [SwiftWriteSTM9]>, 525 SchedVar<SwiftLMAddr10Pred,[SwiftWriteSTM10]>, 526 SchedVar<SwiftLMAddr11Pred,[SwiftWriteSTM11]>, 527 SchedVar<SwiftLMAddr12Pred,[SwiftWriteSTM12]>, 528 SchedVar<SwiftLMAddr13Pred,[SwiftWriteSTM13]>, 529 SchedVar<SwiftLMAddr14Pred,[SwiftWriteSTM14]>, 530 SchedVar<SwiftLMAddr15Pred,[SwiftWriteSTM15]>, 531 SchedVar<SwiftLMAddr16Pred,[SwiftWriteSTM16]>, 532 // Unknow number of registers, just use resources for two registers. 533 SchedVar<NoSchedPred, [SwiftWriteSTM2]> 534 ]>; 535 def : InstRW<[SwiftWriteSTM], 536 (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>; 537 def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteSTM], 538 (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD", 539 "tPUSH")>; 540 541 // LDRLIT pseudo instructions, they expand to LDR + PICADD 542 def : InstRW<[SwiftWriteP2ThreeCycle, WriteALU], 543 (instregex "t?LDRLIT_ga_abs", "t?LDRLIT_ga_pcrel")>; 544 // LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR 545 def : InstRW<[SwiftWriteP2ThreeCycle, SwiftWriteP2ThreeCycle], 546 (instregex "LDRLIT_ga_pcrel_ldr")>; 547 548 // 4.2.26 Branch 549 def : WriteRes<WriteBr, [SwiftUnitP1]> { let Latency = 0; } 550 def : WriteRes<WriteBrL, [SwiftUnitP1]> { let Latency = 2; } 551 def : WriteRes<WriteBrTbl, [SwiftUnitP1, SwiftUnitP2]> { let Latency = 0; } 552 553 // 4.2.27 Not issued 554 def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; } 555 def : InstRW<[WriteNoop], (instregex "t2IT", "IT")>; 556 557 // 4.2.28 Advanced SIMD, Integer, 2 cycle 558 def : InstRW<[SwiftWriteP0TwoCycle], 559 (instregex "VADDv", "VSUBv", "VNEG(s|f|v)", "VADDL", "VSUBL", 560 "VADDW", "VSUBW", "VHADD", "VHSUB", "VRHADD", "VPADDi", 561 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST", 562 "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL(s|u)", "VBIF", 563 "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>; 564 565 def : InstRW<[SwiftWriteP1TwoCycle], 566 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>; 567 568 // 4.2.29 Advanced SIMD, Integer, 4 cycle 569 // 4.2.30 Advanced SIMD, Integer with Accumulate 570 def : InstRW<[SwiftWriteP0FourCycle], 571 (instregex "VABA", "VABAL", "VPADAL", "VRSRA", "VSRA", "VACGE", "VACGT", 572 "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL", 573 "VQRSHL", "VRSHR(u|s)", "VABS(f|v)", "VQABS", "VQNEG", "VQADD", 574 "VQSUB")>; 575 def : InstRW<[SwiftWriteP1FourCycle], 576 (instregex "VRECPE", "VRSQRTE")>; 577 578 // 4.2.31 Advanced SIMD, Add and Shift with Narrow 579 def : InstRW<[SwiftWriteP0P1FourCycle], 580 (instregex "VADDHN", "VSUBHN", "VSHRN")>; 581 def : InstRW<[SwiftWriteP0P1SixCycle], 582 (instregex "VRADDHN", "VRSUBHN", "VRSHRN", "VQSHRN", "VQSHRUN", 583 "VQRSHRN", "VQRSHRUN")>; 584 585 // 4.2.32 Advanced SIMD, Vector Table Lookup 586 foreach Num = 1-4 in { 587 def SwiftWrite#Num#xP1TwoCycle : WriteSequence<[SwiftWriteP1TwoCycle], Num>; 588 } 589 def : InstRW<[SwiftWrite1xP1TwoCycle], 590 (instregex "VTB(L|X)1")>; 591 def : InstRW<[SwiftWrite2xP1TwoCycle], 592 (instregex "VTB(L|X)2")>; 593 def : InstRW<[SwiftWrite3xP1TwoCycle], 594 (instregex "VTB(L|X)3")>; 595 def : InstRW<[SwiftWrite4xP1TwoCycle], 596 (instregex "VTB(L|X)4")>; 597 598 // 4.2.33 Advanced SIMD, Transpose 599 def : InstRW<[SwiftWriteP1FourCycle, SwiftWriteP1FourCycle, 600 SwiftWriteP1TwoCycle/*RsrcOnly*/, SchedReadAdvance<2>], 601 (instregex "VSWP", "VTRN", "VUZP", "VZIP")>; 602 603 // 4.2.34 Advanced SIMD and VFP, Floating Point 604 def : InstRW<[SwiftWriteP0TwoCycle], (instregex "VABS(S|D)$", "VNEG(S|D)$")>; 605 def : InstRW<[SwiftWriteP0FourCycle], 606 (instregex "VCMP(D|S|ZD|ZS)$", "VCMPE(D|S|ZD|ZS)")>; 607 def : InstRW<[SwiftWriteP0FourCycle], 608 (instregex "VADD(S|f)", "VSUB(S|f)", "VABD", "VPADDf", "VMAX", "VMIN", "VPMAX", 609 "VPMIN")>; 610 def : InstRW<[SwiftWriteP0SixCycle], (instregex "VADDD$", "VSUBD$")>; 611 def : InstRW<[SwiftWriteP1EightCycle], (instregex "VRECPS", "VRSQRTS")>; 612 613 // 4.2.35 Advanced SIMD and VFP, Multiply 614 def : InstRW<[SwiftWriteP1FourCycle], 615 (instregex "VMUL(S|v|p|f|s)", "VNMULS", "VQDMULH", "VQRDMULH", 616 "VMULL", "VQDMULL")>; 617 def : InstRW<[SwiftWriteP1FourCycle], 618 (instregex "VMLA", "VMLS", "VNMLA", "VNMLS", "VFMA(S|D)", "VFMS(S|D)", 619 "VFNMA", "VFNMS", "VMLAL", "VMLSL","VQDMLAL", "VQDMLSL")>; 620 def : InstRW<[SwiftWriteP1EightCycle], (instregex "VFMAfd", "VFMSfd")>; 621 def : InstRW<[SwiftWriteP1TwelveCyc], (instregex "VFMAfq", "VFMSfq")>; 622 623 // 4.2.36 Advanced SIMD and VFP, Convert 624 def : InstRW<[SwiftWriteP1FourCycle], (instregex "VCVT", "V(S|U)IT", "VTO(S|U)")>; 625 626 // 4.2.37 Advanced SIMD and VFP, Move 627 def : InstRW<[SwiftWriteP0TwoCycle], 628 (instregex "VMOVv", "VMOV(S|D)$", "VMOV(S|D)cc", 629 "VMVNv", "VMVN(d|q)", 630 "FCONST(D|S)")>; 631 def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VMOVN", "VMOVL")>; 632 def : InstRW<[WriteSequence<[SwiftWriteP0FourCycle, SwiftWriteP1TwoCycle]>], 633 (instregex "VQMOVN")>; 634 def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VDUPLN")>; 635 def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>], 636 (instregex "VDUP(8|16|32)")>; 637 def : InstRW<[SwiftWriteP2ThreeCycle], (instregex "VMOVRS$")>; 638 def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP0TwoCycle]>], 639 (instregex "VMOVSR$", "VSETLN")>; 640 def : InstRW<[SwiftWriteP2ThreeCycle, SwiftWriteP2FourCycle], 641 (instregex "VMOVRR(D|S)$")>; 642 def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>; 643 def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>, 644 WriteSequence<[SwiftWrite1Cycle, SwiftWriteP2FourCycle, 645 SwiftWriteP1TwoCycle]>], 646 (instregex "VMOVSRR$")>; 647 def : InstRW<[WriteSequence<[SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle]>], 648 (instregex "VGETLN(u|i)")>; 649 def : InstRW<[WriteSequence<[SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle, 650 SwiftWriteP01OneCycle]>], 651 (instregex "VGETLNs")>; 652 653 // 4.2.38 Advanced SIMD and VFP, Move FPSCR 654 // Serializing instructions. 655 def SwiftWaitP0For15Cy : SchedWriteRes<[SwiftUnitP0]> { 656 let Latency = 15; 657 let ResourceCycles = [15]; 658 } 659 def SwiftWaitP1For15Cy : SchedWriteRes<[SwiftUnitP1]> { 660 let Latency = 15; 661 let ResourceCycles = [15]; 662 } 663 def SwiftWaitP2For15Cy : SchedWriteRes<[SwiftUnitP2]> { 664 let Latency = 15; 665 let ResourceCycles = [15]; 666 } 667 def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy], 668 (instregex "VMRS")>; 669 def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy], 670 (instregex "VMSR")>; 671 // Not serializing. 672 def : InstRW<[SwiftWriteP0TwoCycle], (instregex "FMSTAT")>; 673 674 // 4.2.39 Advanced SIMD and VFP, Load Single Element 675 def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDRD$", "VLDRS$")>; 676 677 // 4.2.40 Advanced SIMD and VFP, Store Single Element 678 def : InstRW<[SwiftWriteLM4Cy], (instregex "VSTRD$", "VSTRS$")>; 679 680 // 4.2.41 Advanced SIMD and VFP, Load Multiple 681 // 4.2.42 Advanced SIMD and VFP, Store Multiple 682 683 // Resource requirement for permuting, just reserves the resources. 684 foreach Num = 1-28 in { 685 def SwiftVLDMPerm#Num : SchedWriteRes<[SwiftUnitP1]> { 686 let Latency = 0; 687 let NumMicroOps = Num; 688 let ResourceCycles = [Num]; 689 } 690 } 691 692 // Pre RA pseudos - load/store to a Q register as a D register pair. 693 def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDMQIA$", "VSTMQIA$")>; 694 695 // Post RA not modelled accurately. We assume that register use of width 64 696 // bit maps to a D register, 128 maps to a Q register. Not all different kinds 697 // are accurately represented. 698 def SwiftWriteVLDM : SchedWriteVariant<[ 699 // Load of one S register. 700 SchedVar<SwiftLMAddr1Pred, [SwiftWriteLM4Cy]>, 701 // Load of one D register. 702 SchedVar<SwiftLMAddr2Pred, [SwiftWriteLM4Cy, SwiftWriteLM4CyNo]>, 703 // Load of 3 S register. 704 SchedVar<SwiftLMAddr3Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy, 705 SwiftWriteLM13CyNo, SwiftWriteP01OneCycle, 706 SwiftVLDMPerm3]>, 707 // Load of a Q register (not necessarily true). We should not be mapping to 708 // 4 S registers, either. 709 SchedVar<SwiftLMAddr4Pred, [SwiftWriteLM4Cy, SwiftWriteLM4CyNo, 710 SwiftWriteLM4CyNo, SwiftWriteLM4CyNo]>, 711 // Load of 5 S registers. 712 SchedVar<SwiftLMAddr5Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy, 713 SwiftWriteLM13CyNo, SwiftWriteLM14CyNo, 714 SwiftWriteLM17CyNo, SwiftWriteP01OneCycle, 715 SwiftVLDMPerm5]>, 716 // Load of 3 D registers. (Must also be able to handle s register list - 717 // though, not accurate) 718 SchedVar<SwiftLMAddr6Pred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy, 719 SwiftWriteLM10Cy, SwiftWriteLM14CyNo, 720 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 721 SwiftWriteP01OneCycle, SwiftVLDMPerm5]>, 722 // Load of 7 S registers. 723 SchedVar<SwiftLMAddr7Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy, 724 SwiftWriteLM13Cy, SwiftWriteLM14CyNo, 725 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo, 726 SwiftWriteLM21CyNo, SwiftWriteP01OneCycle, 727 SwiftVLDMPerm7]>, 728 // Load of two Q registers. 729 SchedVar<SwiftLMAddr8Pred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy, 730 SwiftWriteLM13Cy, SwiftWriteLM13CyNo, 731 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 732 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 733 SwiftWriteP01OneCycle, SwiftVLDMPerm2]>, 734 // Load of 9 S registers. 735 SchedVar<SwiftLMAddr9Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy, 736 SwiftWriteLM13Cy, SwiftWriteLM14CyNo, 737 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo, 738 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 739 SwiftWriteLM25CyNo, SwiftWriteP01OneCycle, 740 SwiftVLDMPerm9]>, 741 // Load of 5 D registers. 742 SchedVar<SwiftLMAddr10Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy, 743 SwiftWriteLM10Cy, SwiftWriteLM14Cy, 744 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 745 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 746 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 747 SwiftWriteP01OneCycle, SwiftVLDMPerm5]>, 748 // Inaccurate: reuse describtion from 9 S registers. 749 SchedVar<SwiftLMAddr11Pred,[SwiftWriteLM9Cy, SwiftWriteLM10Cy, 750 SwiftWriteLM13Cy, SwiftWriteLM14CyNo, 751 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo, 752 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 753 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 754 SwiftWriteLM25CyNo, SwiftWriteP01OneCycle, 755 SwiftVLDMPerm9]>, 756 // Load of three Q registers. 757 SchedVar<SwiftLMAddr12Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy, 758 SwiftWriteLM11Cy, SwiftWriteLM11Cy, 759 SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, 760 SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, 761 SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, 762 SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, 763 SwiftWriteP01OneCycle, SwiftVLDMPerm3]>, 764 // Inaccurate: reuse describtion from 9 S registers. 765 SchedVar<SwiftLMAddr13Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy, 766 SwiftWriteLM13Cy, SwiftWriteLM14CyNo, 767 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo, 768 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 769 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 770 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 771 SwiftWriteLM25CyNo, SwiftWriteP01OneCycle, 772 SwiftVLDMPerm9]>, 773 // Load of 7 D registers inaccurate. 774 SchedVar<SwiftLMAddr14Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy, 775 SwiftWriteLM10Cy, SwiftWriteLM14Cy, 776 SwiftWriteLM14Cy, SwiftWriteLM14CyNo, 777 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 778 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 779 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 780 SwiftWriteP01OneCycle, SwiftVLDMPerm7]>, 781 SchedVar<SwiftLMAddr15Pred,[SwiftWriteLM9Cy, SwiftWriteLM10Cy, 782 SwiftWriteLM13Cy, SwiftWriteLM14Cy, 783 SwiftWriteLM17Cy, SwiftWriteLM18CyNo, 784 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 785 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 786 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 787 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 788 SwiftWriteLM25CyNo, SwiftWriteP01OneCycle, 789 SwiftVLDMPerm9]>, 790 // Load of 4 Q registers. 791 SchedVar<SwiftLMAddr16Pred,[SwiftWriteLM7Cy, SwiftWriteLM10Cy, 792 SwiftWriteLM11Cy, SwiftWriteLM14Cy, 793 SwiftWriteLM15Cy, SwiftWriteLM18CyNo, 794 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, 795 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, 796 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, 797 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, 798 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, 799 SwiftWriteP01OneCycle, SwiftVLDMPerm4]>, 800 // Unknow number of registers, just use resources for two registers. 801 SchedVar<NoSchedPred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy, 802 SwiftWriteLM13Cy, SwiftWriteLM13CyNo, 803 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 804 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 805 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 806 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 807 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 808 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 809 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 810 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 811 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 812 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 813 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 814 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 815 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 816 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 817 SwiftWriteP01OneCycle, SwiftVLDMPerm2]> 818 ]> { let Variadic = 1; } 819 820 def : InstRW<[SwiftWriteVLDM], (instregex "VLDM[SD](IA|DB)$")>; 821 822 def : InstRW<[SwiftWriteP01OneCycle2x, SwiftWriteVLDM], 823 (instregex "VLDM[SD](IA|DB)_UPD$")>; 824 825 def SwiftWriteVSTM : SchedWriteVariant<[ 826 // One S register. 827 SchedVar<SwiftLMAddr1Pred, [SwiftWriteSTM1]>, 828 // One D register. 829 SchedVar<SwiftLMAddr2Pred, [SwiftWriteSTM1]>, 830 // Three S registers. 831 SchedVar<SwiftLMAddr3Pred, [SwiftWriteSTM4]>, 832 // Assume one Q register. 833 SchedVar<SwiftLMAddr4Pred, [SwiftWriteSTM1]>, 834 SchedVar<SwiftLMAddr5Pred, [SwiftWriteSTM6]>, 835 // Assume three D registers. 836 SchedVar<SwiftLMAddr6Pred, [SwiftWriteSTM4]>, 837 SchedVar<SwiftLMAddr7Pred, [SwiftWriteSTM8]>, 838 // Assume two Q registers. 839 SchedVar<SwiftLMAddr8Pred, [SwiftWriteSTM3]>, 840 SchedVar<SwiftLMAddr9Pred, [SwiftWriteSTM10]>, 841 // Assume 5 D registers. 842 SchedVar<SwiftLMAddr10Pred, [SwiftWriteSTM6]>, 843 SchedVar<SwiftLMAddr11Pred, [SwiftWriteSTM12]>, 844 // Assume three Q registers. 845 SchedVar<SwiftLMAddr12Pred, [SwiftWriteSTM4]>, 846 SchedVar<SwiftLMAddr13Pred, [SwiftWriteSTM14]>, 847 // Assume 7 D registers. 848 SchedVar<SwiftLMAddr14Pred, [SwiftWriteSTM8]>, 849 SchedVar<SwiftLMAddr15Pred, [SwiftWriteSTM16]>, 850 // Assume four Q registers. 851 SchedVar<SwiftLMAddr16Pred, [SwiftWriteSTM5]>, 852 // Asumme two Q registers. 853 SchedVar<NoSchedPred, [SwiftWriteSTM3]> 854 ]> { let Variadic = 1; } 855 856 def : InstRW<[SwiftWriteVSTM], (instregex "VSTM[SD](IA|DB)$")>; 857 858 def : InstRW<[SwiftWriteP01OneCycle2x, SwiftWriteVSTM], 859 (instregex "VSTM[SD](IA|DB)_UPD")>; 860 861 // 4.2.43 Advanced SIMD, Element or Structure Load and Store 862 def SwiftWrite2xP2FourCy : SchedWriteRes<[SwiftUnitP2]> { 863 let Latency = 4; 864 let ResourceCycles = [2]; 865 } 866 def SwiftWrite3xP2FourCy : SchedWriteRes<[SwiftUnitP2]> { 867 let Latency = 4; 868 let ResourceCycles = [3]; 869 } 870 foreach Num = 1-2 in { 871 def SwiftExt#Num#xP0 : SchedWriteRes<[SwiftUnitP0]> { 872 let Latency = 0; 873 let NumMicroOps = Num; 874 let ResourceCycles = [Num]; 875 } 876 } 877 // VLDx 878 // Multiple structures. 879 // Single element structure loads. 880 // We assume aligned. 881 // Single/two register. 882 def : InstRW<[SwiftWriteLM4Cy], (instregex "VLD1(d|q)(8|16|32|64)$")>; 883 def : InstRW<[SwiftWriteLM4Cy, SwiftWriteP01OneCycle], 884 (instregex "VLD1(d|q)(8|16|32|64)wb")>; 885 // Three register. 886 def : InstRW<[SwiftWrite3xP2FourCy], 887 (instregex "VLD1(d|q)(8|16|32|64)T$", "VLD1d64TPseudo")>; 888 def : InstRW<[SwiftWrite3xP2FourCy, SwiftWriteP01OneCycle], 889 (instregex "VLD1(d|q)(8|16|32|64)Twb")>; 890 /// Four Register. 891 def : InstRW<[SwiftWrite2xP2FourCy], 892 (instregex "VLD1(d|q)(8|16|32|64)Q$", "VLD1d64QPseudo")>; 893 def : InstRW<[SwiftWrite2xP2FourCy, SwiftWriteP01OneCycle], 894 (instregex "VLD1(d|q)(8|16|32|64)Qwb")>; 895 // Two element structure loads. 896 // Two/four register. 897 def : InstRW<[SwiftWriteLM9Cy, SwiftExt2xP0, SwiftVLDMPerm2], 898 (instregex "VLD2(d|q|b)(8|16|32)$", "VLD2q(8|16|32)Pseudo$")>; 899 def : InstRW<[SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftExt2xP0, 900 SwiftVLDMPerm2], 901 (instregex "VLD2(d|q|b)(8|16|32)wb", "VLD2q(8|16|32)PseudoWB")>; 902 // Three element structure. 903 def : InstRW<[SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo, 904 SwiftVLDMPerm3, SwiftWrite3xP2FourCy], 905 (instregex "VLD3(d|q)(8|16|32)$")>; 906 def : InstRW<[SwiftWriteLM9Cy, SwiftVLDMPerm3, SwiftWrite3xP2FourCy], 907 (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo$")>; 908 909 def : InstRW<[SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo, 910 SwiftWriteP01OneCycle, SwiftVLDMPerm3, SwiftWrite3xP2FourCy], 911 (instregex "VLD3(d|q)(8|16|32)_UPD$")>; 912 def : InstRW<[SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm3, 913 SwiftWrite3xP2FourCy], 914 (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo_UPD")>; 915 // Four element structure loads. 916 def : InstRW<[SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy, 917 SwiftWriteLM11Cy, SwiftExt2xP0, SwiftVLDMPerm4, 918 SwiftWrite3xP2FourCy], 919 (instregex "VLD4(d|q)(8|16|32)$")>; 920 def : InstRW<[SwiftWriteLM11Cy, SwiftExt2xP0, SwiftVLDMPerm4, 921 SwiftWrite3xP2FourCy], 922 (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo$")>; 923 def : InstRW<[SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy, 924 SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0, 925 SwiftVLDMPerm4, SwiftWrite3xP2FourCy], 926 (instregex "VLD4(d|q)(8|16|32)_UPD")>; 927 def : InstRW<[SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0, 928 SwiftVLDMPerm4, SwiftWrite3xP2FourCy], 929 (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo_UPD")>; 930 931 // Single all/lane loads. 932 // One element structure. 933 def : InstRW<[SwiftWriteLM6Cy, SwiftVLDMPerm2], 934 (instregex "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>; 935 def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm2], 936 (instregex "VLD1(LN|DUP)(d|q)(8|16|32)(wb|_UPD)", 937 "VLD1LNq(8|16|32)Pseudo_UPD")>; 938 // Two element structure. 939 def : InstRW<[SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftExt1xP0, SwiftVLDMPerm2], 940 (instregex "VLD2(DUP|LN)(d|q)(8|16|32|8x2|16x2|32x2)$", 941 "VLD2LN(d|q)(8|16|32)Pseudo$")>; 942 def : InstRW<[SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftWriteP01OneCycle, 943 SwiftExt1xP0, SwiftVLDMPerm2], 944 (instregex "VLD2LN(d|q)(8|16|32)_UPD$")>; 945 def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy, 946 SwiftExt1xP0, SwiftVLDMPerm2], 947 (instregex "VLD2DUPd(8|16|32|8x2|16x2|32x2)wb")>; 948 def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy, 949 SwiftExt1xP0, SwiftVLDMPerm2], 950 (instregex "VLD2LN(d|q)(8|16|32)Pseudo_UPD")>; 951 // Three element structure. 952 def : InstRW<[SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy, SwiftExt1xP0, 953 SwiftVLDMPerm3], 954 (instregex "VLD3(DUP|LN)(d|q)(8|16|32)$", 955 "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo$")>; 956 def : InstRW<[SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy, 957 SwiftWriteP01OneCycle, SwiftExt1xP0, SwiftVLDMPerm3], 958 (instregex "VLD3(LN|DUP)(d|q)(8|16|32)_UPD")>; 959 def : InstRW<[SwiftWriteLM7Cy, SwiftWriteP01OneCycle, SwiftWriteLM8Cy, 960 SwiftWriteLM8Cy, SwiftExt1xP0, SwiftVLDMPerm3], 961 (instregex "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo_UPD")>; 962 // Four element struture. 963 def : InstRW<[SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo, 964 SwiftWriteLM10CyNo, SwiftExt1xP0, SwiftVLDMPerm5], 965 (instregex "VLD4(LN|DUP)(d|q)(8|16|32)$", 966 "VLD4(LN|DUP)(d|q)(8|16|32)Pseudo$")>; 967 def : InstRW<[SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo, 968 SwiftWriteLM10CyNo, SwiftWriteP01OneCycle, SwiftExt1xP0, 969 SwiftVLDMPerm5], 970 (instregex "VLD4(DUP|LN)(d|q)(8|16|32)_UPD")>; 971 def : InstRW<[SwiftWriteLM8Cy, SwiftWriteP01OneCycle, SwiftWriteLM9Cy, 972 SwiftWriteLM10CyNo, SwiftWriteLM10CyNo, SwiftExt1xP0, 973 SwiftVLDMPerm5], 974 (instregex "VLD4(DUP|LN)(d|q)(8|16|32)Pseudo_UPD")>; 975 // VSTx 976 // Multiple structures. 977 // Single element structure store. 978 def : InstRW<[SwiftWrite1xP2], (instregex "VST1d(8|16|32|64)$")>; 979 def : InstRW<[SwiftWrite2xP2], (instregex "VST1q(8|16|32|64)$")>; 980 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2], 981 (instregex "VST1d(8|16|32|64)wb")>; 982 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite2xP2], 983 (instregex "VST1q(8|16|32|64)wb")>; 984 def : InstRW<[SwiftWrite3xP2], 985 (instregex "VST1d(8|16|32|64)T$", "VST1d64TPseudo$")>; 986 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite3xP2], 987 (instregex "VST1d(8|16|32|64)Twb", "VST1d64TPseudoWB")>; 988 def : InstRW<[SwiftWrite4xP2], 989 (instregex "VST1d(8|16|32|64)(Q|QPseudo)$")>; 990 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2], 991 (instregex "VST1d(8|16|32|64)(Qwb|QPseudoWB)")>; 992 // Two element structure store. 993 def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm1], 994 (instregex "VST2(d|b)(8|16|32)$")>; 995 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1], 996 (instregex "VST2(b|d)(8|16|32)wb")>; 997 def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2], 998 (instregex "VST2q(8|16|32)$", "VST2q(8|16|32)Pseudo$")>; 999 def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2], 1000 (instregex "VST2q(8|16|32)wb", "VST2q(8|16|32)PseudoWB")>; 1001 // Three element structure store. 1002 def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2], 1003 (instregex "VST3(d|q)(8|16|32)$", "VST3(d|q)(8|16|32)(oddP|P)seudo$")>; 1004 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2], 1005 (instregex "VST3(d|q)(8|16|32)_UPD", 1006 "VST3(d|q)(8|16|32)(oddP|P)seudo_UPD$")>; 1007 // Four element structure store. 1008 def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2], 1009 (instregex "VST4(d|q)(8|16|32)$", "VST4(d|q)(8|16|32)(oddP|P)seudo$")>; 1010 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm4], 1011 (instregex "VST4(d|q)(8|16|32)_UPD", 1012 "VST4(d|q)(8|16|32)(oddP|P)seudo_UPD$")>; 1013 // Single/all lane store. 1014 // One element structure. 1015 def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm1], 1016 (instregex "VST1LNd(8|16|32)$", "VST1LNq(8|16|32)Pseudo$")>; 1017 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1], 1018 (instregex "VST1LNd(8|16|32)_UPD", "VST1LNq(8|16|32)Pseudo_UPD")>; 1019 // Two element structure. 1020 def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm2], 1021 (instregex "VST2LN(d|q)(8|16|32)$", "VST2LN(d|q)(8|16|32)Pseudo$")>; 1022 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm2], 1023 (instregex "VST2LN(d|q)(8|16|32)_UPD", 1024 "VST2LN(d|q)(8|16|32)Pseudo_UPD")>; 1025 // Three element structure. 1026 def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2], 1027 (instregex "VST3LN(d|q)(8|16|32)$", "VST3LN(d|q)(8|16|32)Pseudo$")>; 1028 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2], 1029 (instregex "VST3LN(d|q)(8|16|32)_UPD", 1030 "VST3LN(d|q)(8|16|32)Pseudo_UPD")>; 1031 // Four element structure. 1032 def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2], 1033 (instregex "VST4LN(d|q)(8|16|32)$", "VST4LN(d|q)(8|16|32)Pseudo$")>; 1034 def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite2xP2, SwiftVLDMPerm2], 1035 (instregex "VST4LN(d|q)(8|16|32)_UPD", 1036 "VST4LN(d|q)(8|16|32)Pseudo_UPD")>; 1037 1038 // 4.2.44 VFP, Divide and Square Root 1039 def SwiftDiv17 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> { 1040 let NumMicroOps = 1; 1041 let Latency = 17; 1042 let ResourceCycles = [1, 15]; 1043 } 1044 def SwiftDiv32 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> { 1045 let NumMicroOps = 1; 1046 let Latency = 32; 1047 let ResourceCycles = [1, 30]; 1048 } 1049 def : InstRW<[SwiftDiv17], (instregex "VDIVS", "VSQRTS")>; 1050 def : InstRW<[SwiftDiv32], (instregex "VDIVD", "VSQRTD")>; 1051 1052 // ===---------------------------------------------------------------------===// 1053 // Floating-point. Map target defined SchedReadWrite to processor specific ones 1054 // 1055 def : SchedAlias<WriteFPCVT, SwiftWriteP1FourCycle>; 1056 def : SchedAlias<WriteFPMOV, SwiftWriteP2ThreeCycle>; 1057 1058 def : SchedAlias<WriteFPALU32, SwiftWriteP0FourCycle>; 1059 def : SchedAlias<WriteFPALU64, SwiftWriteP0SixCycle>; 1060 1061 def : SchedAlias<WriteFPMUL32, SwiftWriteP1FourCycle>; 1062 def : SchedAlias<WriteFPMUL64, SwiftWriteP1SixCycle>; 1063 1064 def : SchedAlias<WriteFPMAC32, SwiftWriteP1FourCycle>; 1065 def : SchedAlias<WriteFPMAC64, SwiftWriteP1FourCycle>; 1066 1067 def : SchedAlias<WriteFPDIV32, SwiftDiv17>; 1068 def : SchedAlias<WriteFPSQRT32, SwiftDiv17>; 1069 1070 def : SchedAlias<WriteFPDIV64, SwiftDiv32>; 1071 def : SchedAlias<WriteFPSQRT64, SwiftDiv32>; 1072 1073 def : ReadAdvance<ReadFPMUL, 0>; 1074 def : ReadAdvance<ReadFPMAC, 0>; 1075 1076 // Overriden via InstRW for this processor. 1077 def : WriteRes<WriteVLD1, []>; 1078 def : WriteRes<WriteVLD2, []>; 1079 def : WriteRes<WriteVLD3, []>; 1080 def : WriteRes<WriteVLD4, []>; 1081 def : WriteRes<WriteVST1, []>; 1082 def : WriteRes<WriteVST2, []>; 1083 def : WriteRes<WriteVST3, []>; 1084 def : WriteRes<WriteVST4, []>; 1085 1086 // Not specified. 1087 def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>; 1088 // Preload. 1089 def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0; 1090 let ResourceCycles = [0]; 1091 } 1092 1093} 1094