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Searched refs:OUT_BATCH (Results 1 – 25 of 47) sorted by relevance

12

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_misc_state.c62 OUT_BATCH(MI_FLUSH); in upload_pipelined_state_pointers()
67 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2)); in upload_pipelined_state_pointers()
72 OUT_BATCH(0); in upload_pipelined_state_pointers()
382 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); in brw_emit_depth_stencil_hiz()
383 OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) | in brw_emit_depth_stencil_hiz()
392 OUT_BATCH(0); in brw_emit_depth_stencil_hiz()
395 OUT_BATCH(((width + tile_x - 1) << 6) | in brw_emit_depth_stencil_hiz()
397 OUT_BATCH(0); in brw_emit_depth_stencil_hiz()
400 OUT_BATCH(tile_x | (tile_y << 16)); in brw_emit_depth_stencil_hiz()
405 OUT_BATCH(0); in brw_emit_depth_stencil_hiz()
[all …]
Dhsw_sol.c104 OUT_BATCH(HSW_MI_MATH | (9 - 2)); in tally_prims_written()
106 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R2)); in tally_prims_written()
107 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
108 OUT_BATCH(MI_MATH_ALU0(SUB)); in tally_prims_written()
109 OUT_BATCH(MI_MATH_ALU2(STORE, R1, ACCU)); in tally_prims_written()
111 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
112 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
113 OUT_BATCH(MI_MATH_ALU0(ADD)); in tally_prims_written()
114 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU)); in tally_prims_written()
127 OUT_BATCH(HSW_MI_MATH | (5 - 2)); in tally_prims_written()
[all …]
Dbrw_compute.c53 OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2)); in prepare_indirect_gpgpu_walker()
54 OUT_BATCH(MI_PREDICATE_SRC0 + 4); in prepare_indirect_gpgpu_walker()
55 OUT_BATCH(0u); in prepare_indirect_gpgpu_walker()
56 OUT_BATCH(MI_PREDICATE_SRC1 + 0); in prepare_indirect_gpgpu_walker()
57 OUT_BATCH(0u); in prepare_indirect_gpgpu_walker()
58 OUT_BATCH(MI_PREDICATE_SRC1 + 4); in prepare_indirect_gpgpu_walker()
59 OUT_BATCH(0u); in prepare_indirect_gpgpu_walker()
67 OUT_BATCH(GEN7_MI_PREDICATE | in prepare_indirect_gpgpu_walker()
78 OUT_BATCH(GEN7_MI_PREDICATE | in prepare_indirect_gpgpu_walker()
89 OUT_BATCH(GEN7_MI_PREDICATE | in prepare_indirect_gpgpu_walker()
[all …]
Dgen7_misc_state.c106 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); in gen7_emit_depth_stencil_hiz()
109 OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) | in gen7_emit_depth_stencil_hiz()
120 OUT_BATCH(0); in gen7_emit_depth_stencil_hiz()
124 OUT_BATCH(((width - 1) << 4) | in gen7_emit_depth_stencil_hiz()
129 OUT_BATCH(((depth - 1) << 21) | in gen7_emit_depth_stencil_hiz()
134 OUT_BATCH(0); in gen7_emit_depth_stencil_hiz()
137 OUT_BATCH((depth - 1) << 21); in gen7_emit_depth_stencil_hiz()
142 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); in gen7_emit_depth_stencil_hiz()
143 OUT_BATCH(0); in gen7_emit_depth_stencil_hiz()
144 OUT_BATCH(0); in gen7_emit_depth_stencil_hiz()
[all …]
Dgen8_depth_state.c65 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2)); in emit_depth_packets()
66 OUT_BATCH(depth_surface_type << 29 | in emit_depth_packets()
75 OUT_BATCH(0); in emit_depth_packets()
76 OUT_BATCH(0); in emit_depth_packets()
78 OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod); in emit_depth_packets()
79 OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb); in emit_depth_packets()
80 OUT_BATCH(0); in emit_depth_packets()
81 OUT_BATCH(((depth - 1) << 21) | in emit_depth_packets()
87 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2)); in emit_depth_packets()
88 OUT_BATCH(0); in emit_depth_packets()
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Dgen6_depth_state.c112 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); in gen6_emit_depth_stencil_hiz()
115 OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) | in gen6_emit_depth_stencil_hiz()
127 OUT_BATCH(0); in gen6_emit_depth_stencil_hiz()
131 OUT_BATCH(((width - 1) << 6) | in gen6_emit_depth_stencil_hiz()
136 OUT_BATCH((depth - 1) << 21 | in gen6_emit_depth_stencil_hiz()
141 OUT_BATCH(0); in gen6_emit_depth_stencil_hiz()
145 OUT_BATCH(0); in gen6_emit_depth_stencil_hiz()
167 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); in gen6_emit_depth_stencil_hiz()
168 OUT_BATCH(depth_mt->hiz_buf->surf.row_pitch - 1); in gen6_emit_depth_stencil_hiz()
173 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); in gen6_emit_depth_stencil_hiz()
[all …]
Dbrw_pipe_control.c165 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2)); in brw_emit_pipe_control()
166 OUT_BATCH(flags); in brw_emit_pipe_control()
170 OUT_BATCH(0); in brw_emit_pipe_control()
171 OUT_BATCH(0); in brw_emit_pipe_control()
173 OUT_BATCH(imm); in brw_emit_pipe_control()
174 OUT_BATCH(imm >> 32); in brw_emit_pipe_control()
196 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2)); in brw_emit_pipe_control()
197 OUT_BATCH(flags); in brw_emit_pipe_control()
201 OUT_BATCH(0); in brw_emit_pipe_control()
203 OUT_BATCH(imm); in brw_emit_pipe_control()
[all …]
Dgen8_multisample_state.c83 OUT_BATCH(_3DSTATE_SAMPLE_PATTERN << 16 | (9 - 2)); in gen8_emit_3dstate_sample_pattern()
86 OUT_BATCH(brw_multisample_positions_16x[0]); /* positions 3, 2, 1, 0 */ in gen8_emit_3dstate_sample_pattern()
87 OUT_BATCH(brw_multisample_positions_16x[1]); /* positions 7, 6, 5, 4 */ in gen8_emit_3dstate_sample_pattern()
88 OUT_BATCH(brw_multisample_positions_16x[2]); /* positions 11, 10, 9, 8 */ in gen8_emit_3dstate_sample_pattern()
89 OUT_BATCH(brw_multisample_positions_16x[3]); /* positions 15, 14, 13, 12 */ in gen8_emit_3dstate_sample_pattern()
92 OUT_BATCH(brw_multisample_positions_8x[1]); /* sample positions 7654 */ in gen8_emit_3dstate_sample_pattern()
93 OUT_BATCH(brw_multisample_positions_8x[0]); /* sample positions 3210 */ in gen8_emit_3dstate_sample_pattern()
96 OUT_BATCH(brw_multisample_positions_4x); in gen8_emit_3dstate_sample_pattern()
99 OUT_BATCH(brw_multisample_positions_1x_2x); in gen8_emit_3dstate_sample_pattern()
Dbrw_binding_tables.c89 OUT_BATCH(packet_name << 16 | (2 - 2)); in brw_upload_binding_table()
93 OUT_BATCH(stage_state->bind_bo_offset); in brw_upload_binding_table()
252 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2)); in gen4_upload_binding_table_pointers()
253 OUT_BATCH(brw->vs.base.bind_bo_offset); in gen4_upload_binding_table_pointers()
254 OUT_BATCH(0); /* gs */ in gen4_upload_binding_table_pointers()
255 OUT_BATCH(0); /* clip */ in gen4_upload_binding_table_pointers()
256 OUT_BATCH(0); /* sf */ in gen4_upload_binding_table_pointers()
257 OUT_BATCH(brw->wm.base.bind_bo_offset); in gen4_upload_binding_table_pointers()
282 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | in gen6_upload_binding_table_pointers()
287 OUT_BATCH(brw->vs.base.bind_bo_offset); /* vs */ in gen6_upload_binding_table_pointers()
[all …]
Dintel_blit.c109 OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2)); in set_blitter_tiling()
110 OUT_BATCH(0); in set_blitter_tiling()
111 OUT_BATCH(0); in set_blitter_tiling()
112 OUT_BATCH(0); in set_blitter_tiling()
114 OUT_BATCH(0); in set_blitter_tiling()
116 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); in set_blitter_tiling()
117 OUT_BATCH(BCS_SWCTRL); in set_blitter_tiling()
118 OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 | in set_blitter_tiling()
622 OUT_BATCH(CMD | (length - 2)); in intelEmitCopyBlit()
623 OUT_BATCH(BR13 | (uint16_t)dst_pitch); in intelEmitCopyBlit()
[all …]
Dgen7_urb.c122 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2)); in gen7_emit_push_constant_state()
123 OUT_BATCH(vs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); in gen7_emit_push_constant_state()
126 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_HS << 16 | (2 - 2)); in gen7_emit_push_constant_state()
127 OUT_BATCH(hs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); in gen7_emit_push_constant_state()
130 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_DS << 16 | (2 - 2)); in gen7_emit_push_constant_state()
131 OUT_BATCH(ds_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); in gen7_emit_push_constant_state()
134 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_GS << 16 | (2 - 2)); in gen7_emit_push_constant_state()
135 OUT_BATCH(gs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); in gen7_emit_push_constant_state()
138 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2)); in gen7_emit_push_constant_state()
139 OUT_BATCH(fs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); in gen7_emit_push_constant_state()
[all …]
Dhsw_queryobj.c77 OUT_BATCH(HSW_MI_MATH | (1 + ARRAY_SIZE(maths) - 2)); in mult_gpr0_by_80()
80 OUT_BATCH(maths[m]); in mult_gpr0_by_80()
102 OUT_BATCH(HSW_MI_MATH | (1 + ARRAY_SIZE(maths) - 2)); in keep_gpr0_lower_n_bits()
105 OUT_BATCH(maths[m]); in keep_gpr0_lower_n_bits()
139 OUT_BATCH(HSW_MI_MATH | (cmd_len - 2)); in shl_gpr0_by_30_bits()
142 OUT_BATCH(shl_maths[m]); in shl_gpr0_by_30_bits()
181 OUT_BATCH(HSW_MI_MATH | (1 + ARRAY_SIZE(maths) - 2)); in gpr0_to_bool()
184 OUT_BATCH(maths[m]); in gpr0_to_bool()
237 OUT_BATCH(HSW_MI_MATH | (1 + ARRAY_SIZE(maths) - 2)); in calc_overflow_for_stream()
240 OUT_BATCH(maths[m]); in calc_overflow_for_stream()
[all …]
Dgen7_l3_state.c148 OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2)); in setup_l3_config()
151 OUT_BATCH(GEN7_L3SQCREG1); in setup_l3_config()
152 OUT_BATCH((devinfo->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT : in setup_l3_config()
161 OUT_BATCH(GEN7_L3CNTLREG2); in setup_l3_config()
162 OUT_BATCH((has_slm ? GEN7_L3CNTLREG2_SLM_ENABLE : 0) | in setup_l3_config()
168 OUT_BATCH(GEN7_L3CNTLREG3); in setup_l3_config()
169 OUT_BATCH(SET_FIELD(cfg->n[GEN_L3P_IS], GEN7_L3CNTLREG3_IS_ALLOC) | in setup_l3_config()
180 OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2)); in setup_l3_config()
181 OUT_BATCH(HSW_SCRATCH1); in setup_l3_config()
182 OUT_BATCH(has_dc ? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE); in setup_l3_config()
[all …]
Dgen6_sol.c420 OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2)); in brw_begin_transform_feedback()
421 OUT_BATCH(0); /* SVBI 0 */ in brw_begin_transform_feedback()
422 OUT_BATCH(0); /* starting index */ in brw_begin_transform_feedback()
423 OUT_BATCH(brw_obj->max_index); in brw_begin_transform_feedback()
432 OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2)); in brw_begin_transform_feedback()
433 OUT_BATCH(i << SVB_INDEX_SHIFT); in brw_begin_transform_feedback()
434 OUT_BATCH(0); /* starting index */ in brw_begin_transform_feedback()
435 OUT_BATCH(0xffffffff); in brw_begin_transform_feedback()
502 OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2)); in brw_resume_transform_feedback()
503 OUT_BATCH(0); /* SVBI 0 */ in brw_resume_transform_feedback()
[all …]
Dintel_batchbuffer.c764 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2)); in brw_finish_batch()
765 OUT_BATCH(brw->cc.state_offset | 1); in brw_finish_batch()
1208 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2)); in load_sized_register_mem()
1209 OUT_BATCH(reg + i * 4); in load_sized_register_mem()
1216 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2)); in load_sized_register_mem()
1217 OUT_BATCH(reg + i * 4); in load_sized_register_mem()
1255 OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2)); in brw_store_register_mem32()
1256 OUT_BATCH(reg); in brw_store_register_mem32()
1261 OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); in brw_store_register_mem32()
1262 OUT_BATCH(reg); in brw_store_register_mem32()
[all …]
/external/mesa3d/src/gallium/drivers/i915/
Di915_state_emit.c68 OUT_BATCH(MI_FLUSH | FLUSH_MAP_CACHE); in emit_flush()
70 OUT_BATCH(MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE); in emit_flush()
172 OUT_BATCH(fixup_imm); in emit_immediate_s5()
192 OUT_BATCH(imm); in emit_immediate_s6()
207 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | in emit_immediate()
215 OUT_BATCH(0); in emit_immediate()
225 OUT_BATCH(i915->current.immediate[i]); in emit_immediate()
242 OUT_BATCH(i915->current.dynamic[i]); in emit_dynamic()
274 OUT_BATCH(_3DSTATE_BUF_INFO_CMD); in emit_static()
275 OUT_BATCH(i915->current.cbuf_flags); in emit_static()
[all …]
Di915_clear.c133 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); in i915_clear_emit()
135 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS); in i915_clear_emit()
136 OUT_BATCH(CLEARPARAM_WRITE_COLOR | CLEARPARAM_CLEAR_RECT); in i915_clear_emit()
138 OUT_BATCH(clear_color); in i915_clear_emit()
139 OUT_BATCH(clear_depth); in i915_clear_emit()
141 OUT_BATCH(clear_color8888); in i915_clear_emit()
143 OUT_BATCH(clear_stencil); in i915_clear_emit()
145 OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5); in i915_clear_emit()
153 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS); in i915_clear_emit()
154 OUT_BATCH((clear_params & ~CLEARPARAM_WRITE_COLOR) | in i915_clear_emit()
[all …]
Di915_prim_emit.c83 OUT_BATCH( fui(attrib[0]) ); in emit_hw_vertex()
87 OUT_BATCH( fui(attrib[0]) ); in emit_hw_vertex()
88 OUT_BATCH( fui(attrib[1]) ); in emit_hw_vertex()
92 OUT_BATCH( fui(attrib[0]) ); in emit_hw_vertex()
93 OUT_BATCH( fui(attrib[1]) ); in emit_hw_vertex()
94 OUT_BATCH( fui(attrib[2]) ); in emit_hw_vertex()
98 OUT_BATCH( fui(attrib[0]) ); in emit_hw_vertex()
99 OUT_BATCH( fui(attrib[1]) ); in emit_hw_vertex()
100 OUT_BATCH( fui(attrib[2]) ); in emit_hw_vertex()
101 OUT_BATCH( fui(attrib[3]) ); in emit_hw_vertex()
[all …]
Di915_blit.c78 OUT_BATCH(CMD); in i915_fill_blit()
79 OUT_BATCH(BR13); in i915_fill_blit()
80 OUT_BATCH((y << 16) | x); in i915_fill_blit()
81 OUT_BATCH(((y + h) << 16) | (x + w)); in i915_fill_blit()
83 OUT_BATCH(color); in i915_fill_blit()
150 OUT_BATCH(CMD); in i915_copy_blit()
151 OUT_BATCH(BR13); in i915_copy_blit()
152 OUT_BATCH((dst_y << 16) | dst_x); in i915_copy_blit()
153 OUT_BATCH((dst_y2 << 16) | dst_x2); in i915_copy_blit()
155 OUT_BATCH((src_y << 16) | src_x); in i915_copy_blit()
[all …]
Di915_prim_vbuf.c396 OUT_BATCH((i+0) | (i+1) << 16); in draw_arrays_generate_indices()
398 OUT_BATCH(i); in draw_arrays_generate_indices()
403 OUT_BATCH((i-1) | (i+0) << 16); in draw_arrays_generate_indices()
404 OUT_BATCH((i-1) | ( start) << 16); in draw_arrays_generate_indices()
409 OUT_BATCH((i+0) | (i+1) << 16); in draw_arrays_generate_indices()
410 OUT_BATCH((i+3) | (i+1) << 16); in draw_arrays_generate_indices()
411 OUT_BATCH((i+2) | (i+3) << 16); in draw_arrays_generate_indices()
416 OUT_BATCH((i+0) | (i+1) << 16); in draw_arrays_generate_indices()
417 OUT_BATCH((i+3) | (i+2) << 16); in draw_arrays_generate_indices()
418 OUT_BATCH((i+0) | (i+3) << 16); in draw_arrays_generate_indices()
[all …]
/external/mesa3d/src/mesa/drivers/dri/i915/
Di830_vtbl.c304 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); in i830_emit_invarient_state()
305 OUT_BATCH(0); in i830_emit_invarient_state()
307 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); in i830_emit_invarient_state()
308 OUT_BATCH(0); in i830_emit_invarient_state()
310 OUT_BATCH(_3DSTATE_DFLT_Z_CMD); in i830_emit_invarient_state()
311 OUT_BATCH(0); in i830_emit_invarient_state()
313 OUT_BATCH(_3DSTATE_FOG_MODE_CMD); in i830_emit_invarient_state()
314 OUT_BATCH(FOGFUNC_ENABLE | in i830_emit_invarient_state()
316 OUT_BATCH(0); in i830_emit_invarient_state()
317 OUT_BATCH(0); in i830_emit_invarient_state()
[all …]
Di915_vtbl.c181 OUT_BATCH(_3DSTATE_AA_CMD | in i915_emit_invarient_state()
186 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); in i915_emit_invarient_state()
187 OUT_BATCH(0); in i915_emit_invarient_state()
189 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); in i915_emit_invarient_state()
190 OUT_BATCH(0); in i915_emit_invarient_state()
192 OUT_BATCH(_3DSTATE_DFLT_Z_CMD); in i915_emit_invarient_state()
193 OUT_BATCH(0); in i915_emit_invarient_state()
196 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS | in i915_emit_invarient_state()
203 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD); in i915_emit_invarient_state()
204 OUT_BATCH(0); in i915_emit_invarient_state()
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Dintel_blit.c321 OUT_BATCH(CMD | (8 - 2)); in intelEmitCopyBlit()
322 OUT_BATCH(BR13 | (uint16_t)dst_pitch); in intelEmitCopyBlit()
323 OUT_BATCH((dst_y << 16) | dst_x); in intelEmitCopyBlit()
324 OUT_BATCH((dst_y2 << 16) | dst_x2); in intelEmitCopyBlit()
328 OUT_BATCH((src_y << 16) | src_x); in intelEmitCopyBlit()
329 OUT_BATCH((uint16_t)src_pitch); in intelEmitCopyBlit()
495 OUT_BATCH(CMD | (6 - 2)); in intelClearWithBlit()
496 OUT_BATCH(BR13); in intelClearWithBlit()
497 OUT_BATCH((y1 << 16) | x1); in intelClearWithBlit()
498 OUT_BATCH((y2 << 16) | x2); in intelClearWithBlit()
[all …]
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_ioctl.c102 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); in radeonEmitScissor()
103 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] | RADEON_SCISSOR_ENABLE); in radeonEmitScissor()
104 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); in radeonEmitScissor()
105 OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) | in radeonEmitScissor()
107 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); in radeonEmitScissor()
108 OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2) << 16) | in radeonEmitScissor()
113 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); in radeonEmitScissor()
114 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & ~RADEON_SCISSOR_ENABLE); in radeonEmitScissor()
137 OUT_BATCH(rmesa->ioctl.vertex_offset); in radeonEmitVbufPrim()
139 OUT_BATCH(vertex_nr); in radeonEmitVbufPrim()
[all …]
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_cmdbuf.c132 OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA | in r200EmitVbufPrim()
144 OUT_BATCH(R200_VF_PRIM_WALK_IND | in r200FireEB()
150 OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); in r200FireEB()
151 OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); in r200FireEB()
152 OUT_BATCH((vertex_count + 1)/2); in r200FireEB()
215 OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0)); in r200EmitMaxVtxIndex()
216 OUT_BATCH(count); in r200EmitMaxVtxIndex()
233 OUT_BATCH(1); in r200EmitVertexAOS()
234 OUT_BATCH(vertex_size | (vertex_size << 8)); in r200EmitVertexAOS()
252 OUT_BATCH(nr); in r200EmitAOS()
[all …]

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