| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFrameLowering.cpp | 159 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
160 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in emitPrologue()
165 .addReg(OffsetReg); in emitPrologue()
200 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
202 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in emitEpilogue()
209 .addReg(OffsetReg); in emitEpilogue()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | ShadowCallStack.cpp | 92 const MCPhysReg OffsetReg = X86::R11; in addProlog() local
100 .addDef(OffsetReg) in addProlog()
101 .addReg(OffsetReg, RegState::Undef) in addProlog()
102 .addReg(OffsetReg, RegState::Undef); in addProlog()
105 OffsetReg) in addProlog()
109 BuildMI(MBB, MBBI, DL, TII->get(X86::MOV64rm)).addDef(OffsetReg), X86::GS, in addProlog()
110 OffsetReg); in addProlog()
113 OffsetReg) in addProlog()
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| D | X86CallLowering.cpp | 116 unsigned OffsetReg = MRI.createGenericVirtualRegister(SType); in getStackAddress() local
117 MIRBuilder.buildConstant(OffsetReg, Offset); in getStackAddress()
120 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFrameLowering.cpp | 168 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
169 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in emitPrologue()
174 .addReg(OffsetReg); in emitPrologue()
224 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
226 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in emitEpilogue()
233 .addReg(OffsetReg); in emitEpilogue()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.h | 41 unsigned OffsetReg,
47 unsigned OffsetReg,
246 unsigned OffsetReg) const;
254 unsigned OffsetReg) const;
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| D | R600InstrInfo.cpp | 1059 unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1060 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1065 OffsetReg); in expandPostRAPseudo()
1073 unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1074 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1080 OffsetReg); in expandPostRAPseudo()
1136 unsigned OffsetReg) const { in buildIndirectWrite()
1137 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1143 unsigned OffsetReg, in buildIndirectWrite() argument
1154 AMDGPU::AR_X, OffsetReg); in buildIndirectWrite()
[all …]
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| D | SIRegisterInfo.cpp | 293 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in materializeFrameBaseRegister() local
295 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in materializeFrameBaseRegister()
299 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
346 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in resolveFrameIndex() local
351 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in resolveFrameIndex()
355 .addReg(OffsetReg, RegState::Kill) in resolveFrameIndex()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.h | 52 unsigned OffsetReg,
58 unsigned OffsetReg,
248 unsigned OffsetReg) const;
256 unsigned OffsetReg) const;
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| D | R600InstrInfo.cpp | 1041 unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1042 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1047 OffsetReg); in expandPostRAPseudo()
1055 unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1056 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1062 OffsetReg); in expandPostRAPseudo()
1117 unsigned OffsetReg) const { in buildIndirectWrite()
1118 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1124 unsigned OffsetReg, in buildIndirectWrite() argument
1135 R600::AR_X, OffsetReg); in buildIndirectWrite()
[all …]
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| D | AMDGPUCallLowering.cpp | 60 unsigned OffsetReg = MRI.createGenericVirtualRegister(LLT::scalar(64)); in lowerParameterPtr() local
61 MIRBuilder.buildConstant(OffsetReg, Offset); in lowerParameterPtr()
63 MIRBuilder.buildGEP(DstReg, KernArgSegmentVReg, OffsetReg); in lowerParameterPtr()
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| D | SIRegisterInfo.cpp | 321 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in materializeFrameBaseRegister() local
325 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in materializeFrameBaseRegister()
331 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
674 unsigned OffsetReg = AMDGPU::M0; in spillSGPR() local
726 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), OffsetReg) in spillSGPR()
730 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in spillSGPR()
737 .addReg(OffsetReg, RegState::Kill) // soff in spillSGPR()
844 unsigned OffsetReg = AMDGPU::M0; in restoreSGPR() local
888 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), OffsetReg) in restoreSGPR()
892 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in restoreSGPR()
[all …]
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| D | AMDGPUInstructionSelector.cpp | 556 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectSMRD() local
557 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), OffsetReg) in selectSMRD()
562 .addReg(OffsetReg) in selectSMRD()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 130 unsigned OffsetReg; member
176 return Mem.OffsetReg; in getMemOffsetReg()
615 Op->Mem.OffsetReg = 0; in MorphToMemImm()
623 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
627 Op->Mem.OffsetReg = OffsetReg; in MorphToMemRegReg()
639 Op->Mem.OffsetReg = 0; in MorphToMemRegImm()
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| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 115 unsigned OffsetReg; member
161 return Mem.OffsetReg; in getMemOffsetReg()
600 Op->Mem.OffsetReg = 0; in MorphToMemImm()
608 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
612 Op->Mem.OffsetReg = OffsetReg; in MorphToMemRegReg()
624 Op->Mem.OffsetReg = 0; in MorphToMemRegImm()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 139 unsigned OffsetReg = MRI.createGenericVirtualRegister(s64); in getStackAddress() local
140 MIRBuilder.buildConstant(OffsetReg, Offset); in getStackAddress()
143 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 159 unsigned OffsetReg = MRI.createGenericVirtualRegister(s32); in getStackAddress() local
160 MIRBuilder.buildConstant(OffsetReg, Offset); in getStackAddress()
163 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 422 unsigned OffsetReg = 0; in ReduceLoadStore() local
425 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
453 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
456 MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); in ReduceLoadStore()
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| D | Thumb2InstrInfo.cpp | 472 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg(); in rewriteT2FrameIndex() local
473 if (OffsetReg != 0) { in rewriteT2FrameIndex()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 104 unsigned OffsetReg = MRI.createGenericVirtualRegister(s32); in getStackAddress() local
105 MIRBuilder.buildConstant(OffsetReg, Offset); in getStackAddress()
108 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| D | Thumb2SizeReduction.cpp | 557 unsigned OffsetReg = 0; in ReduceLoadStore() local
561 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
596 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
599 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 239 unsigned OffsetReg; member
299 return Mem.OffsetReg; in getMemOffsetReg()
468 Op->Mem.OffsetReg = offsetReg; in MorphToMEMrr()
477 Op->Mem.OffsetReg = Sparc::G0; // always 0 in CreateMEMr()
489 Op->Mem.OffsetReg = 0; in MorphToMEMri()
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 212 unsigned OffsetReg; member
271 return Mem.OffsetReg; in getMemOffsetReg()
440 Op->Mem.OffsetReg = offsetReg; in MorphToMEMrr()
449 Op->Mem.OffsetReg = Sparc::G0; // always 0 in CreateMEMr()
461 Op->Mem.OffsetReg = 0; in MorphToMEMri()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 528 unsigned OffsetReg = 0; in ReduceLoadStore() local
532 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
567 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
570 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
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| D | Thumb2InstrInfo.cpp | 540 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg(); in rewriteT2FrameIndex() local
541 if (OffsetReg != 0) { in rewriteT2FrameIndex()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringARM32.cpp | 5490 const Variable *OffsetReg, int16_t OffsetRegShAmt, in dumpAddressOpt() argument
5506 if (OffsetReg) in dumpAddressOpt()
5507 OffsetReg->dump(Func); in dumpAddressOpt()
5566 Variable **OffsetReg, int32_t OffsetRegShamt, in matchCombinedBaseIndex() argument
5572 if (*OffsetReg != nullptr) in matchCombinedBaseIndex()
5598 *OffsetReg = Var2; in matchCombinedBaseIndex()
5605 Variable **OffsetReg, OperandARM32::ShiftKind *Kind, in matchShiftedOffsetReg() argument
5614 if (*OffsetReg == nullptr) in matchShiftedOffsetReg()
5616 auto *IndexInst = VMetadata->getSingleDefinition(*OffsetReg); in matchShiftedOffsetReg()
5619 assert(!VMetadata->isMultiDef(*OffsetReg)); in matchShiftedOffsetReg()
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