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Searched refs:OpReg (Results 1 – 24 of 24) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86FastISel.cpp1091 unsigned OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local
1092 if (OpReg == 0) return false; in X86SelectBranch()
1094 .addReg(OpReg).addImm(1); in X86SelectBranch()
1114 unsigned OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1115 if (OpReg == 0) return false; in X86SelectBranch()
1118 .addReg(OpReg).addImm(1); in X86SelectBranch()
1127 unsigned CReg = 0, OpReg = 0; in X86SelectShift() local
1133 case Instruction::LShr: OpReg = X86::SHR8rCL; break; in X86SelectShift()
1134 case Instruction::AShr: OpReg = X86::SAR8rCL; break; in X86SelectShift()
1135 case Instruction::Shl: OpReg = X86::SHL8rCL; break; in X86SelectShift()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86FastISel.cpp1736 unsigned OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local
1737 if (OpReg == 0) return false; in X86SelectBranch()
1740 .addReg(OpReg).addImm(1); in X86SelectBranch()
1773 unsigned OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1774 if (OpReg == 0) return false; in X86SelectBranch()
1777 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) { in X86SelectBranch()
1778 unsigned KOpReg = OpReg; in X86SelectBranch()
1779 OpReg = createResultReg(&X86::GR32RegClass); in X86SelectBranch()
1781 TII.get(TargetOpcode::COPY), OpReg) in X86SelectBranch()
1783 OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, /*Kill=*/true, in X86SelectBranch()
[all …]
DX86SpeculativeLoadHardening.cpp1763 unsigned OpReg = Op->getReg(); in hardenLoadAddr() local
1764 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr()
1802 .addReg(OpReg); in hardenLoadAddr()
1833 .addReg(OpReg); in hardenLoadAddr()
1846 .addReg(OpReg); in hardenLoadAddr()
1855 .addReg(OpReg) in hardenLoadAddr()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp341 unsigned OpReg = MI.getOperand(0).getReg(); in narrowScalar() local
343 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalar()
350 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalar()
394 unsigned OpReg = MI.getOperand(2).getReg(); in narrowScalar() local
396 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalar()
404 } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalar()
407 DstRegs.push_back(OpReg); in narrowScalar()
426 unsigned SegReg = OpReg; in narrowScalar()
430 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); in narrowScalar()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp1654 unsigned OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local
1655 if (OpReg == 0) return false; in X86SelectBranch()
1657 .addReg(OpReg).addImm(1); in X86SelectBranch()
1690 unsigned OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1691 if (OpReg == 0) return false; in X86SelectBranch()
1694 .addReg(OpReg).addImm(1); in X86SelectBranch()
1702 unsigned CReg = 0, OpReg = 0; in X86SelectShift() local
1708 case Instruction::LShr: OpReg = X86::SHR8rCL; break; in X86SelectShift()
1709 case Instruction::AShr: OpReg = X86::SAR8rCL; break; in X86SelectShift()
1710 case Instruction::Shl: OpReg = X86::SHL8rCL; break; in X86SelectShift()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp300 unsigned OpReg = MI->getOperand(I).getReg(); in optimizeSDPattern() local
302 if (!TRI->isVirtualRegister(OpReg)) in optimizeSDPattern()
305 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
DARMInstructionSelector.cpp852 unsigned OpReg = I.getOperand(2).getReg(); in select() local
853 unsigned Size = MRI.getType(OpReg).getSizeInBits(); in select()
DARMFastISel.cpp1278 unsigned OpReg = getRegForValue(TI->getOperand(0)); in SelectBranch() local
1279 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
1282 .addReg(OpReg).addImm(1)); in SelectBranch()
/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp306 unsigned OpReg = MI->getOperand(I).getReg(); in optimizeSDPattern() local
308 if (!TRI->isVirtualRegister(OpReg)) in optimizeSDPattern()
311 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
DARMFastISel.cpp1277 unsigned OpReg = getRegForValue(TI->getOperand(0)); in SelectBranch() local
1278 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
1281 .addReg(OpReg).addImm(1)); in SelectBranch()
/external/swiftshader/third_party/subzero/src/
DIceAssemblerMIPS32.cpp163 IValueT encodeRegister(const Operand *OpReg, RegSetWanted WantedRegSet, in encodeRegister() argument
166 if (encodeOperand(OpReg, Reg, WantedRegSet) != true) in encodeRegister()
172 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName, in encodeGPRegister() argument
174 return encodeRegister(OpReg, WantGPRegs, RegName, InstName); in encodeGPRegister()
177 IValueT encodeFPRegister(const Operand *OpReg, const char *RegName, in encodeFPRegister() argument
179 return encodeRegister(OpReg, WantFPRegs, RegName, InstName); in encodeFPRegister()
DIceAssemblerARM32.cpp540 IValueT encodeRegister(const Operand *OpReg, RegSetWanted WantedRegSet, in encodeRegister() argument
543 if (encodeOperand(OpReg, Reg, WantedRegSet) != EncodedAsRegister) in encodeRegister()
549 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName, in encodeGPRegister() argument
551 return encodeRegister(OpReg, WantGPRegs, RegName, InstName); in encodeGPRegister()
554 IValueT encodeSRegister(const Operand *OpReg, const char *RegName, in encodeSRegister() argument
556 return encodeRegister(OpReg, WantSRegs, RegName, InstName); in encodeSRegister()
559 IValueT encodeDRegister(const Operand *OpReg, const char *RegName, in encodeDRegister() argument
561 return encodeRegister(OpReg, WantDRegs, RegName, InstName); in encodeDRegister()
564 IValueT encodeQRegister(const Operand *OpReg, const char *RegName, in encodeQRegister() argument
566 return encodeRegister(OpReg, WantQRegs, RegName, InstName); in encodeQRegister()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DFastISel.cpp796 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); in SelectFNeg() local
797 if (OpReg == 0) return false; in SelectFNeg()
804 ISD::FNEG, OpReg, OpRegIsKill); in SelectFNeg()
818 ISD::BITCAST, OpReg, OpRegIsKill); in SelectFNeg()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1478 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); in selectFNeg() local
1479 if (!OpReg) in selectFNeg()
1486 OpReg, OpRegIsKill); in selectFNeg()
1501 ISD::BITCAST, OpReg, OpRegIsKill); in selectFNeg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineInstr.cpp1634 unsigned OpReg = MO.getReg(); in clearRegisterKills() local
1635 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) in clearRegisterKills()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1683 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); in selectFNeg() local
1684 if (!OpReg) in selectFNeg()
1691 OpReg, OpRegIsKill); in selectFNeg()
1706 ISD::BITCAST, OpReg, OpRegIsKill); in selectFNeg()
/external/llvm/lib/CodeGen/
DMachineInstr.cpp2013 unsigned OpReg = MO.getReg(); in clearRegisterKills() local
2014 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) in clearRegisterKills()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp3968 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList() local
3969 if (OpReg == Reg) in checkLowRegisterList()
3972 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
3982 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg() local
3983 if (OpReg == Reg) in listContainsReg()
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp176 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT() local
178 getVectorRegSize(OpReg)/ScalarVT.getSizeInBits()); in getRegOperandVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp218 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts() local
219 return getVectorRegSize(OpReg) / ScalarSize; in getRegOperandNumElts()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMFastISel.cpp1168 unsigned OpReg = getRegForValue(TI->getOperand(0)); in SelectBranch() local
1171 .addReg(OpReg).addImm(1)); in SelectBranch()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp3452 unsigned OpReg = Op.getReg(); in legalizeGenericOperand() local
3456 RI.getRegClassForReg(MRI, OpReg), OpSubReg); in legalizeGenericOperand()
3469 MachineInstr *Def = MRI.getVRegDef(OpReg); in legalizeGenericOperand()
3475 FoldImmediate(*Copy, *Def, OpReg, &MRI); in legalizeGenericOperand()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp6291 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList() local
6292 if (OpReg == Reg) in checkLowRegisterList()
6295 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
6305 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg() local
6306 if (OpReg == Reg) in listContainsReg()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp6106 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList() local
6107 if (OpReg == Reg) in checkLowRegisterList()
6110 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
6120 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg() local
6121 if (OpReg == Reg) in listContainsReg()